HMC439 seems to respond to signal amplitudes?

Hi,

The HMC439 is very similar to the HMC4069. In the data sheet of the HMC4069, at page 6 there is this typical performance plot:

I use the HMC439 eval board. I apply L1R and  L1V clocks different by a small margin. For example, I played with L1R=50.000010 MHz and VCO=50MHz. I used an AD9545 eval board to generate them, so they had the same CML amplitude. I reproduced the plot above on the oscilloscope. If the plot matched the behavior from the plot, I considered the chip as being OK.

In lieu of amplitude variation, I simply muted one of the inputs. In this case, ND2 or NU2 go to 5V and when the clock is unmuted, that particular signal remains there. I considered this to be OK.

My recommendation to you is to replicate this test. If you get such outputs from the chip, then the chip is OK and this how it is supposed to function.

  Petre

Interesting, thank you for the example - this is what I was looking for! At 100MHz|+11Hz at REF, things actually look quite similar: 

Furthermore, sending the loop filter through signal generator's FM input actually does achieve phase lock! So the thing must be working. It seems to also work across a larger range of powers, so no issues there...

When I start reducing the frequency, things break down and invert around 55MHz given everything else equal: 

no phase lock can be achieved from here on.

The question is, why does it flip - the transformer at ref should be broadband enough, resistive splitter even less of an issue and both inputs look fine on scope...

Hi,

let me see if I understand:

- you tested 100MHz clocks and the PLL you put together locked.

- then you powered down/up and tested 55MHz clocks and NU and ND switched behavior. 

The fact that NU and ND switched behavior is what I wanted to convey when I said in my previous response that ND or NU go to 5V.

So I believe that this behavior is to be expected. For every phase difference between REF and VCO, the devices may output two different NU or ND situations (the inverted behavior you also found). I believe the choice between them is determined by the sequence of REF and VCO being available at the HMC439 after power up.

I also like to think that between 100MHz testing  and 55MHz testing, the chip should be powered down. I do not believe keeping the device powered up while changing REF and VCO frequency is something that happens in reality. So if you did not powered down/up the device between these two tests, please do this. I hope this will then make the PLL to lock.

Petre 

So, after further testing, it seems like it was a matter of insufficient input power - increasing the VCO input from -8dBm to about -5dBm resulted in a stable lock at lower frequencies... Though it seems more then needed according to the datasheet. Possibly, some interference from the switcher in the supply circuit might play a role when the RF input is too weak, although I use extra filtering and post-regulation and don't see much on the scope...

I'm thinking if introducing balanced drive of VCO/nVCO & REF/nREF through transformers might improve sensitivity/EMI immunity, as I have to use one for isolation purposes anyway...

HI,

usually differential signals are better than single ended ones, but I'm speaking in general, not for this particular device. I see the typical application circuit from the data sheet also uses single ended clocks, so using differential clocks is not an absolute must. 

Note both REF and VCO circuits have 50ohm input resistors.

Petre

Thank you for pointing this out - I was aware of this, this is why I didn't implement it in the first place. Looking at the schematics again though, I'm a bit unsure about the impedance of NVCO/NREF itself - it seems to be clipped to a constant voltage by the diodes without resistor in series. My plan was to use a 1:1 transformer with a center tap on the secondary grounded and differential line decoupled by Cs as in the single ended case. It does however seem like the lower part of the coil will see a different impedance due to the diodes then the upped does. Or am I wrong?

HI,

The 50ohm internal load seems done for a single ended clock. I believe that even if the R and V inputs are differential, they kind of recommend using single ended ones. Look at the typical PLL application circuit in the data sheet:

Even if the divide by 2 IC can output a differential clock, they still used a single ended connection between the IC and the HMC439

Bottom line: try with the differential transformer or even a balun, but I believe the HMC439 in the end likes single ended input clocks.

Petre