We have designed the circuit for ADF4002 as PFD (with reference to Fig 21. from datasheet). In our setup we are using minicircuits ZOS-150 VCO, we need to stabilize the beat frequency of 1 MHz from two VCOs.
Vt is the tuning voltage to the VCO, is added with voltage from the ADF 4002 ( pin 2 Cp), after filter stages for frequency stabilization.
We designed the circuit base on Evaluation Board User Guide (UG -108). We tested the above circuit in the test setup (CE - Vcc)., with signal generators, ( RF in -10MHz sinusoidal, REF in - 10MHz). At pin2 Cp we see a ramp signal of 100 KHz. We have designed the loop filter in ADISIm Pll and tested the circuit. At the output of the loop filter, we see the same ramp instead of a stable Vt which has to be fed to the VCO.
We have progammed the chip with SPI interfact, programmed the N and R register frequency division value to 1.
We are attaching the Schematic and ADIsim Pll loop filter design for your reference
Kindly look into it and send us feed back accordingly. 
PDF
Rgds
Meena
