Power sequence

You can keep ctrl and enable pin at 0V (logic low) before Vdd/Vss turn on.

Hi,

Thks for the prompt reply. I have further queries.

1. My enable pin is currently tied to Vdd. In this case, only ctrl pin will be at 0V before Vdd/ Vss is turned on. Will tgis also works? 

2. I am feeding the ctrl pin from a fpga output pin. I can limit the current from the fpga output to <3mA. Will this also prevent the chip from being damaged.

1. We don't recommend applying 5V to EN pin before Vdd. If EN pin is also connected to FPGA, I suggest pulling it down until power up.

2. This may be unnecessary if you wait supplies turn on and apply CTRL voltage. However, it's always good idea to use current limit in this scenario. You can also set a lower limit like 500uA. 3mA is absolute maximum rating it's not a recommended operating condition.

Hi, 

Thks for the advice. I am using a single fpga output pin to drive 4 adrf5020. Do u forsee any problem if I limit the current to 500uA. Will the current be sufficient..

This current limit should keep digital pins safe. I see you're careful about you switching speed, you may check risetime of ctrl signal after setting the current limit. If it's significantly slowing down, you may consider increasing current limit until 3 mA.