Hello, I would like to configure an FMCW waveform with 5902, with a specific bandwidth of 50M, rise time of 140us, fall time of 20us, idle time of 80us, cycle of 240us, and a 50MHz crystal oscillator. The initialization sequence I changed according to the datasheet has been unable to make 5092 work. Here is my initialization sequence：
Step Register Code Code Description
1 R7 0x02000007 Master reset
2 R11 0x0000002B Reset the counters
3 R11 0x0000110B Enable counters
4 R13 0x0018050D Enable ramp divider
5 R10 0x1D32A64A Reserved
6 R9 0x2A20B929 VCO calibration setup
7 R8 0x40003E88 Set the VCO frequency calibration divider clock to 100 kHz
8 R0 0x800FE520 Power up the device and LO
Delay of 10 μs
9 R7 0x0100a027 PFD = 25 MHz, CLK1 = 2048
10 R6 0x00000006 Set the LSB FRAC = 0
11 R5 0x21E08005 N = 240
12 R4 0x00002004 Set the ATEST pin to highimpedance
13 R3 0x0189FB43 Sets the I/O level to 3.3 V,RAMPSTATUS TO MUXOIUT to MUXOUT
14 R2 0x00020642 Set ADC clock to 1 MHz
15 R1 0xFFF7eFa1 Set the transmitter amplitude level
16 R0 0x801FE720 Start the VCO frequency calibration
Delay of 1200 μs
17 R0 0x801FE560 Turn Tx1 on, Tx2 off, and LO on
18 R0 0x801FED60 Tx1 amplitude calibration
Delay of 500 μs
21 R17 0x00000011 Reserved
22 R16 0x00000010 Ramp delay register
23 R15 0x000008CF Load step register with STEP SEL = 0, step word is 70
24 R15 0x0200014F Load step register with STEP SEL = 1, step word is 10
25 R15 0x040008CF Load step register with STEP SEL = 2, step word is 70
26 R15 0x0600014F Load step register with STEP SEL = 3, step word is 10
27 R14 0x01203AAE Load deviation register with DEV SEL = 0, DEV = 469, DEVoffset = 9
28 R14 0x033E664E Load deviation register with DEV SEL = 1, dev word = -3278, DEV offset = 9
29 R14 0x05203AAE Load deviation register with DEV SEL = 2, dev word = 469, DEV offset = 9
30 R14 0x073E664E Load deviation register with DEV SEL = 3, dev word = -3278, DEV offset = 9
31 R13 0x0018050D Load the clock register with CLK DIV SEL = 0, CLK2 0 = 10
32 R13 0x0018052D Load the clock register with CLK DIV SEL = 1, CLK2 1 = 10
33 R13 0x0018054D Load the clock register with CLK DIV SEL = 2, CLK2 2 = 10
34 R13 0x0018056D Load the clock register with CLKDIV SEL = 3, CLK2 3 = 10
35 R12 0x004F000C Charge pump current = 2.24 mA
36 R9 0x2800B929 Normal Operation
37 R7 0x0100A027 PFD = 50 MHz, CLK1 = 10
38 R6 0x00000006 Set the LSB FRAC = 0
39 R5 0x21E08005 INT = 480, lock to 24GHz
40 R4 0x00002004 Ramp down to MUXOUT
41 R3 0x018FB43 I/O voltage level to 3.3 V Delay of 100 μs
42 R11 0x0000110B Select ramp mode
Who can help me? Thank you.
