Frequency Drift of ADF4159

Hi,

Did you use on-board crystal oscillator as reference? XO has natural drift and specturm analyzer has own oscillator. the frequency value of the XO and oscillator in the spectrum might in the slightly different time domain.

Or you signal generator for reference are connected to spectrum analyzer with BNC connector for 10MHz to bring these two instruments into the same time domain. 

ADF4159 is a PLL and locks VCO to the reference. as long as reference is fixed there should not be frequency drift.

Thanks,

Emrecan

Hi,

Firstly, thank you for the response.

We are using a  custom designed PCB and the reference clock was given externally. The reference clock used was 100 MHz.

I've verified the reference clock output on spectrum to see if there was any drift. The signal was clean and no drift observed (checked in low spans such as 1kHz with 3Hz RBW).

While verifying the schematic of our PCB, I've noticed that the "RFout/4" pin of HMC507 chip was not terminated with 50 ohm. Is there any chance that the frequency drift was happening because of this?

Also during the endurance test for 3 hours, we have observed that the frequency was drifting from negative to positive and vice versa with respective to center frequency on spectrum analyzer. Do you still think the drift was because of reference clock?

Please guide me through this and how to resolve the issue.

Thank you,

G.A.R.

Hi,

Firstly, thank you for the response.

We are using a  custom designed PCB and the reference clock was given externally. The reference clock used was 100 MHz.

I've verified the reference clock output on spectrum to see if there was any drift. The signal was clean and no drift observed (checked in low spans such as 1kHz with 3Hz RBW).

While verifying the schematic of our PCB, I've noticed that the "RFout/4" pin of HMC507 chip was not terminated with 50 ohm. Is there any chance that the frequency drift was happening because of this?

Also during the endurance test for 3 hours, we have observed that the frequency was drifting from negative to positive and vice versa with respective to center frequency on spectrum analyzer. Do you still think the drift was because of reference clock?

Please guide me through this and how to resolve the issue.

Thank you,

G.A.R.

Hi G.A.R

Termination is important for proper PLL operation. Loading at the RFOUT/4 might harm the loop performance. However, as long as PLL is locked, termination shouldn't affect the frequency accuracy.

What is the reference source? If it is signal generator, Are signal generator and spectrum analyzer is connected with  BNC cable to bring both devices into the same time domain?

This behavior seems like XO drift either in the signal generator or spectrum analyzer. You need to connect two instruments together To synchronize the time base of these instruments.

If reference is standalone XO, then this drift is definitely XO drift and this is expected. For example, XO has 10ppm accuracy PLL output also will have 10ppm accuracy at 7 GHZ, this drift is around 70kHz. If XO drifts 0.1ppm during the endurance tests, PLL output will shift 700Hz. 

Thanks,

Emrecan

Hello Emrecan,

Thank you for responding.

We have terminated the RFout/4 and the drift issue still persists.

The reference source is external, from an inhouse designed card that is embedded with OCX chip i.e., NM-100M-6812.

We have actually observed XO drift in low spans but ignored it as it drifted like 2Hz after 15 minutes of endurance test. Does that impact the drift in PLL output?

We will perform the synchronization of OCXO output and PLL output to bring them in same time domain and share our observations here soon.

Meanwhile, I'm attaching few images which are from schematic of custom designed card that contains PLL and VCO chip. Please go through and lemme know if you find any abnormality. 

Thanks,

G.A.R.

Hi G.A.R, 

Your reference is 100MHz. It shifts 2Hz during endurance tests that mean it has 0.02ppm drift. 

This drift will be observed at the PLL output too.  0.02ppm drift will correspond to 143.4 Hz frequency drift at 7170 MHz. 

Does the drift go higher than this value? I read it has around 100Hz drift from the spectrum capture.

Thanks,

Emrecan

Hello Emrecan,

Sorry for the late reply. 

Yes, during long hours of endurance tests, the team has observed that the drift was happening beyond a value you mentioned.

In fact, the peak signal was observed to be shifting from positive to negative and vice versa, as if like a pendulum but happening slowly. 

With that observation, I doubt that the PLL itself causing some kind of issue but not the reference input clock. What do you think?

Also studied that, the drifts can be due to operating the PLL at high temperatures which caused instability and lead to this drift issue. What's your view on it? FYI, We have not used any DC fans in testbench setup.

Thank you,

G.A.R.