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Frequency Drift of ADF4159

Category: Datasheet/Specs
Product Number: ADF4159

Hello,

I've custom PCB embedded with ADF4159 PLL chip and VCO chip used was HMC507.

After writing the PLL registers using a microcontroller via SPI, the board was getting locked at desired frequency i.e., 7170 MHz.

When observed on spectrum analyzer in low spans, noticed that there was frequency drift during endurance test for an hour.

For reference, I'm attaching the loop filter design that I've generated on ADISimPLL and applied in PCB.

Also attaching an image file of observation of frequency drift on a spectrum analyzer.

Can your expertise guide me why this drift is happening and what are the ways to resolve this? It will be much helpful.

Thank you,

G.A.R.

Parents
  • Hi,

    Did you use on-board crystal oscillator as reference? XO has natural drift and specturm analyzer has own oscillator. the frequency value of the XO and oscillator in the spectrum might in the slightly different time domain.

    Or you signal generator for reference are connected to spectrum analyzer with BNC connector for 10MHz to bring these two instruments into the same time domain. 

    ADF4159 is a PLL and locks VCO to the reference. as long as reference is fixed there should not be frequency drift.

    Thanks,

    Emrecan

  • Hi,

    Firstly, thank you for the response.

    We are using a  custom designed PCB and the reference clock was given externally. The reference clock used was 100 MHz.

    I've verified the reference clock output on spectrum to see if there was any drift. The signal was clean and no drift observed (checked in low spans such as 1kHz with 3Hz RBW).

    While verifying the schematic of our PCB, I've noticed that the "RFout/4" pin of HMC507 chip was not terminated with 50 ohm. Is there any chance that the frequency drift was happening because of this?

    Also during the endurance test for 3 hours, we have observed that the frequency was drifting from negative to positive and vice versa with respective to center frequency on spectrum analyzer. Do you still think the drift was because of reference clock?

    Please guide me through this and how to resolve the issue.

    Thank you,

    G.A.R.

Reply
  • Hi,

    Firstly, thank you for the response.

    We are using a  custom designed PCB and the reference clock was given externally. The reference clock used was 100 MHz.

    I've verified the reference clock output on spectrum to see if there was any drift. The signal was clean and no drift observed (checked in low spans such as 1kHz with 3Hz RBW).

    While verifying the schematic of our PCB, I've noticed that the "RFout/4" pin of HMC507 chip was not terminated with 50 ohm. Is there any chance that the frequency drift was happening because of this?

    Also during the endurance test for 3 hours, we have observed that the frequency was drifting from negative to positive and vice versa with respective to center frequency on spectrum analyzer. Do you still think the drift was because of reference clock?

    Please guide me through this and how to resolve the issue.

    Thank you,

    G.A.R.

Children
  • Hi G.A.R

    Termination is important for proper PLL operation. Loading at the RFOUT/4 might harm the loop performance. However, as long as PLL is locked, termination shouldn't affect the frequency accuracy.

    What is the reference source? If it is signal generator, Are signal generator and spectrum analyzer is connected with  BNC cable to bring both devices into the same time domain?

    This behavior seems like XO drift either in the signal generator or spectrum analyzer. You need to connect two instruments together To synchronize the time base of these instruments.

    If reference is standalone XO, then this drift is definitely XO drift and this is expected. For example, XO has 10ppm accuracy PLL output also will have 10ppm accuracy at 7 GHZ, this drift is around 70kHz. If XO drifts 0.1ppm during the endurance tests, PLL output will shift 700Hz. 

    Thanks,

    Emrecan