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PLL Design problem

Category: Hardware
Product Number: AD9901

  1. I'm working on a PLL design with AD9901, GPS 10KHz reference signal, and 10MHz cristal ocxo divided by 1000 as VCO.

    I'm having trouble gettimg AD9901 to lock. I'm just getting a 500mV maximum output from it. All signals are TTL. I have researched and there's almost no literature or examples of use. GPS' logic one is roughly  2.2V, could that be a problem? Behaviour is erratic, sometimes I get that 200mV signal and sometimes nothing. It was supposed to deliver at least 3.2V

    Any suggestions? I even tried to inject two square signals, 50% duty cycle,  0° phase offset from an AWG, with no sucess