Occasional unlock of ADF4106 in an FSK modulation circuit

Hi, 

I have a few questions about PLL ADF4106 used in an FSK modulation circuit.

Fig.1 Block Diagram of FSK modulation circuit

- Used in our FSK transmitter products manufactured for over 10 years.
- A few defective products were found of which transmission modulation spectrum was abnormal.
- Solved by replacing the PLL ICs.
- Spectrum abnormality does not occur when the modulation data is PN 9, but occurs when the data is PN 15 or PN 23, which has a series of 0s and 1s.
- In the most recent lot, approximately 40% of the products were defective with the same symptoms.

Please see Fig.2, 2A, 2B, and 2C.

Fig. 2 VTune & LD under the modulation signal of 0.5Hz square wave

Fig. 2A   Magnified part A in Fig. 2

Fig. 2B  Magnified part B in Fig. 2

Fig. 2C  Magnified part C in Fig. 2

- Occasionally the lock comes loose. Loss of lock occurs after a series of "H" or "L" in the modulation signal.
- Under the modulation signal of a 0.5Hz square wave, VTUNE may drop to 0V 3.5ms after the falling edge of the modulation signal and become unlocked. (Fig.2B)
- However, the drop doesn't happen every time after the falling edge. (Fig.2A)
- VTUNE changes immediately after the rise and fall of the modulation signal, and the pull-in ends in 1ms to become a steady state.
- If Anti Backlash Pulse Width (ABPW) of 2.9ns or 6.0ns is set for ADF4106, the unlock phenomenon do not occur.
- When CW is generated, unlock does not occur even if ABPW is 1.3ns.

My Surmise
- When the PLL locks and continues to stay in the PFD dead zone, a reset will occur.
- The reset takes only once after entering the dead zone from outside the dead zone.

Questions
- Is the above reasoning correct?
- What is the purpose of resetting (or kickoff)? Unlike PD, PFD does not cause false lock in which the phase differs by pi from the correct phase (Fig.3, and Fig.4). So a reset doesn't seem necessary.

Fig. 3  Phase Detector (PD) chararacteristics

Fig. 4  Phase Frequency Detector (PFD) chararacteristics

- What are the conditions for applying a reset?
- How does the PLL distinguish between false lock and correct lock?
- Why doesn't the reset (kickoff) work in CW?
- What are the side effects of increasing ABPW? What kind of performance will be degraded?
- Are there other solutions besides increase of ABPW?
- Some devices occur a reset and some do not. Why does it vary?