The issue of difficulty in achieving lock when connecting the ADF4159 and ADF5901 via the SDP-S board.

Hi, 

When you disable the ramp and set the ADF4159 and ADF5901 to fixed 24GHz , can ADF4159 achieve lock consistently? 

Thanks,

Emrecan

Hi Emrecan，

    Currently, it's quite strange. No matter how I set it up, there's no output from ADF5901. The voltage fluctuates between 0.43 and 0.61.

    Thanks

    Best Regards

    opensky

Hi Opensky,

Can we make sure that SPI communication is present with the chips? 

- Can you try changing MUXOUT of ADF4159 to logic low and logic high and measure the MUXOUT (Pin 17) of the ADF4159? If read voltage value follows the SPI settings, we are sure that SPI communication is present to ADF4159

- Repeat above test for ADF5901

- For ADF5904, power down and power up all the channels and observe the current consumption. If current consumptions tracks the register settings, we are sure that SPI is present . 

I assume that 0.43 and 0.63 value are the voltage value at Vtune input of the ADF5901. It is low for a fixed frequency operation. We expect 1.5 - 1.8 volt around this pin. 

Next step is debugging the N Divider and R divider outputs. Please follow steps in the below file for PLL Debug.

After ADF4159 and ADF5901 are locked to a fixed frequency, we can debug ramp generation issues. 

Thanks,

Emrecan

Hi Emrecan,

     --MUXOUT of ADF4159:

              DVdd:1.94V/GND:0.14V

              R-Divider:100MHz,0.69V

              Disgital Lock Detect:1.94V

    --MUXOUT of ADF5901:

             If IO Level:1.8V

              Logic High:3.43V/Logic Low:1.84V/R-Divider:100MHz,3.47V

             If IO Level:3.3V

              Logic High:2.07V/Logic Low:0.12V/R-Divider:100MHz,1.83V

   --ADF5904:

              By controlling CE, the current has a significant change from 0.67A to 0.13A.（ ADF5901 and ADF5904 share one CE control, while ADF4159 has another CE control.）

        The Vtune value sometimes reads 3.3V and other times 1.7V, but the RF output of ADF5901 is consistently absent.

         We will continue to debug according to the provided documentation.

         Thanks

         Best Regards 

        Opensky

Hi Opensky,

Thanks for the measurements. Does the R-Divider of the ADF5901 output 100MHz? According to screen shot you have sent, reference frequency is 50MHz and R doubler is disabled. measuring 100MHz from R divider output is strange. Can you make sure R divider and R doubler is set correctly in ADF5901.

Thanks,

Emrecan

Hi Emrecan,

    The board we designed had the MUX of ADF4159 and ADF5901 connected together. Now they have been separated. The R Divider output of ADF4159 is 100MHz, but the R Divider output of ADF5901 is sometimes 1.5MHz and sometimes not detectable at all, while it should normally be 50MHz.

   Their settings are as shown in the figure below：

    Thanks

    Best Regards

    opensky