Post Go back to editing

ADF4117: MUXOUT before configuration

Category: Hardware
Product Number: ADF4117

Hello,

I have a question about the phenomenon of MUXOUT of ADF4117.
The customer's products is in mass production, but there was a AD8342 that did not appear to be normal.
After being powered on, the MUXOUT output high(open) but it goes to low after about 5ms from powered on.
In the thread (ez.analog.com/.../muxout-control-of-adf4117), it said that the MUXOUT is selected 3-THATE OUPUT after POR.
If so, the MUXOUT should output high(open) until configuration via SPI.
Other ADF4117 holds the MUXOUT to high(open) until configuration.
And, the cusotmer select MUXOUT to ANALOG LOCK DETECT but the MUXOUT keeps low(close) after configuration.

Figure 1 is the MUXOUT output of this ADF4117 and Figure 2 is the other's.
This ADF4117 outputs true frequency somewhare in starting up the customer's product.
(The MUXOUT monitor signal is pulled up by the supply of the next circuit. This supply reached 3.3V before starting the 3.3V for ADF4117.)


The question from the customer:
Q1. What is the reason for this phenomenon?
       Is a different condition in the start up?
Q2. Can I use this device ongoingly or should it be replaced?

The customer has found this on the device selected to check performance but has not checked all other ADF4117s.
They have not been able to verify if there are other ADF4117s that behave in a similar manner.

Should we simply assume that the MUXOUT of this ADF4117 is faulty?

Best regards,

y_suzuki

  • Hi suzuki,

    Are the NG chip and the OK chip both on identical boards? any hardware, software, and production lot differences between the chips?
    Does muxout output have a 10k pull-up resistor?
    Is the initial latch sequence is same?

    Regards,
    Burhan

  • Hello Burhan,

    It is a production model, so it has the same board and the same configuration sequence.
    I will confirm the date code of the NG chip and the Other OK chip.
    MUXOUT is pulled up by about 100k ohm resister.
    (please see the following figure)




    Best regards,

    y_suzuki

  • Hi suzuki,

    Thank you for your explanation. Could they measure the lock time? do both chips have the same lock time and only the NG part's lock detect signal behaviour is unsuitable?
    In general, when everything is similar, it is not expected to act like this, the chip might be damaged. ın some cases lock time could be changed but 5 ms is too much while the total lock time is couple of hundred microseconds for this chip. So ı could not advise changing the settling time settings. we may need to understand if the frequency settling is similar for both chips. they can rework the NG chip with the OK chip and test it to see if the problem follows the chip. 

    Regards,
    Burhan