Hey,
I'm using the admv4640 with the following configurations:
{ADMV4640_SPI_CONFIG_1_ADD, 0x99}, // SPI configuration
{ADMV4640_SPI_CONFIG_1_ADD, 0x18}, // SPI configuration
{ADMV4640_MUTE_UNLOCK_ADD, 0x00}, // Not mute if PLL unlock
{ADMV4640_FRAC1_L_ADD, 0x00}, // PLL Frac-N Word
{ADMV4640_FRAC1_M_ADD, 0x00}, // PLL Frac-N Word
{ADMV4640_FRAC1_H_ADD, 0x00}, // PLL Frac-N Word
{ADMV4640_MOD_L_ADD, 0x01}, // DSM MODULUS LSB
{ADMV4640_MOD_H_ADD, 0x00}, // DSM MODULUS MSB
{ADMV4640_SYNTH_ADD, 0x01}, // Enable Feedback Divider, Disable 2x Prescalar
{ADMV4640_R_DIV_ADD, 0x01}, // PLL R Divider Word
{ADMV4640_REFERENCE_ADD, 0x04}, // Disable reference doubler and reference doubler
{ADMV4640_SD_CTRL_ADD, 0x00}, // Disable Sigma Delta
{ADMV4640_MULTI_FUNC_SYNTH_CTRL_022B_ADD, 0x01}, // ADI's internal register
{ADMV4640_MULTI_FUNC_SYNTH_CTRL_022D_ADD, 0xA1}, // Enable Phase Detector and Charge Pump
{ADMV4640_CP_CURR_ADD, 0xC8}, // Set charge pump current
{ADMV4640_VCO_FSM_ADD, 0x27}, // Set charge pump bleed current
{ADMV4640_VCO_BAND_DIV_ADD, 0x05},
{ADMV4640_VCO_TIMEOUT_L_ADD, 0x02},
{ADMV4640_VCO_TIMEOUT_H_ADD, 0x00},
{ADMV4640_VCO_TIMEOUT_H_ADD, 0x00},
{ADMV4640_INT_H_ADD, 0x01}, // PLL Integer-N Word
{ADMV4640_INT_L_ADD, 0x80}, // PLL Integer-N Word
{ADMV4640_LOCK_DETECT_CONFIG_ADD, 0x40}, // Optimze lock detection timing
{ADMV4640_MUTE_MASK_CONTROL_ADD, 0x03}, // Set Mute Mask
{ADMV4640_ON_MASK_CONTROL_ADD, 0x03}, // Set RX ON Mask
{ADMV4640_ADC_CONTROL_ADD, 0xC7}, // Configure ADC
{ADMV4640_RFBIAS_CONTROL1_ADD, 0x02}, // Set IF bias current
{ADMV4640_RFBIAS_CONTROL2_ADD, 0x33}, // Set LNA bias current
{ADMV4640_RFBIAS_CONTROL3_ADD, 0x48}, // Set LO bias current
{ADMV4640_MIXER_CONTROL1_ADD, 0x09}, // Set Mixer bias current
{ADMV4640_MIXER_CONTROL2_ADD, 0x09}, // Set Mixer bias current
{ADMV4640_MUXOUT_ADD, 0x01}, // Set MUXOUTPLLLock
{ADMV4640_MUTE_UNLOCK_ADD, 0x01}, // Mute if PLL unlock
{ADMV4640_REG024C_ADD, 0x40}, // Optimze PLL timing
{ADMV4640_VCO_FSM_ADD, 0x90}, // Optimze PLL timing
{ADMV4640_REG021A_ADD, 0x38}, // Optimze PLL timing
I'm using a reference clock of 10 Mhz.
I'm using Revgo's configurations requirements.
However, The pll lock bit on register 0x24D is never set.
What am I doing wrong?
Tnx in advance.