What are the setup and hold requirements for SDI on ADMV4640? I'm trying to use a SPI controller block in a Xilinx Kria K26I FPGA SOM to talk to the ADMV4640, but find that I need to delay the SDI signal relative to the clock (sacrificing some setup time to get larger hold time) in order to get working communication. I can not find any explanation for this in the datasheets, so I'm wondering if there are some undocumented rules I have to follow here...
The SPI IP block I'm using is the AXI Quad SPI (3.2) IP from Xilinx, running in Standard rather than Quad mode. This IP generates a "perfect" SPI waveform, with setup and hold times both being nominally half the clock period. So at 3.125 MHz SPI clock (tCLK = 320 ns), the waveform looks like this:
Now, the only SPI timing information I can find in the ADMV4640 datasheet is that a "typical" SPI frequency is 20 MHz, which I interpret to mean that clocks up to at least this rate should work.
The datasheet also references the ADI-SPI Technical Specification, which contain the following additional information:
- Hold time (tDH) should be less than 25% of the clock period.
- Setup time (tDS) should be less than 25% of the clock period.
- There is no minimum interface speed.
So the conclusion I could draw from this is that the timing shown above should work. However it does not. But I can get working communication by simply delaying the SDI signal with a chain of FDRE:s before routing it out to the pin. This decreases the setup time and increases the hold time, while still staying within the limits stated above. Here are some delays I tested (see below for logic analyzer grabs):
| Nominal timing | Measured timing | Observed behaviour | |||||
| tCLK | SDI delay | tDS | tDH | tDS | tDH | tS | |
| 320 ns | 0 ns | 160 ns (50%) | 160 ns (50%) | 168 ns | 160 ns | 4398 ns | Does not work |
| 320 ns | 40 ns | 120 ns (37%) | 200 ns (63%) | 128 ns | 200 ns | 4430 ns | Does not work |
| 320 ns | 80 ns | 80 ns (25%) | 240 ns (75%) | 88 ns | 242 ns | 4228 ns | Works reliably |
The observation "does not work" means that the ADMV4640 does not reply to a request to read register 0. This register is known to contain the value 0x18, which I can also verify by switching to the 80 ns delay setting and reading out the correct value without having to write the register first.
The observation "Works reliably" means that not only can I read the value 0x18 from register 0, I can also write arbitrary values to arbitrary registers and read them back, multiple times.
For the measurements I used a logic analyzer with a time resolution of 2 ns, connected close to the ADMV4640 pins. This is what it looks like:
No delay, does not work (no response from the ADMV4640 on SDO).
40 ns delay, does not work (no response from the ADMV4640 on SDO).
80 ns delay, works reliably. (Readout of 0x18 from register 0 shown.)
So in summary, am I actually expected to add 160 ns (50% of tCLK) more hold time than what the ADI-SPI Technical Specification says is necessary? Or is there some other timing constraint in play here? As I said the measurements above are taken close to the chip pins, but even so the margin to 25% setup/hold is 80 ns at delay=0, so clock skew can not be a reasonable explanation (all wire lengths are well below 1m).