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Generating 1 GHz Ramp

Category: Datasheet/Specs
Product Number: ADF4159

Hello everyone,

I am wondering if I can use the ADF4158/4159 PLL to generate ramp signals up to 1 GHz? If so, how would I do that?

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  • I am wondering if there is a DAC/DDS which can create a 250 MHz or greater ramp signal in time with an integrated PLL? I would also like to use an external signal as reference (yellow trace below).

  • Hi, 

    Thanks for clarifying the ramp requirements.

    ADF4159/8 only generates frequency domain modulations. For amplitude domain modulations, you need a DDS. 

    AD9914/5 are suitable candidates. 

    You can use one of the ADF4160-X PLL/VCO integrated synthesizers to generate clock for DSS from your reference. Then you can feed this clock to AD9914 to generate the desired output profile. 

    Thanks,

    Emrecan 

  • Hello,

    The AD9914 was actually the first device I looked at. However, I noticed that the digital ramp generator (DRG) in the manual operated at 1/24th the frequency of the DAC clock. This would not be fast enough to generate ramps @ 250 MHz. This is how I interpreted it. Am I missing something?

    I was also looking at the AD9166 DC to 9 GHz vector signal generator Eval board used in conjunction with the ADS7-V2EBZ FPGA. My understanding of this duo is that I can use the DPGDownloader to generate vectors and upload them to the AD9166 via the FPGA. Would this allow me to create the amplitude ramp signals I need, or is this overkill? Could I get away with a faster but cheaper DAC? Is using the laser signal in the above picture as a phase reference still possible? From my understanding, the answer is yes, but I want to make sure I am not missing anything.

Reply
  • Hello,

    The AD9914 was actually the first device I looked at. However, I noticed that the digital ramp generator (DRG) in the manual operated at 1/24th the frequency of the DAC clock. This would not be fast enough to generate ramps @ 250 MHz. This is how I interpreted it. Am I missing something?

    I was also looking at the AD9166 DC to 9 GHz vector signal generator Eval board used in conjunction with the ADS7-V2EBZ FPGA. My understanding of this duo is that I can use the DPGDownloader to generate vectors and upload them to the AD9166 via the FPGA. Would this allow me to create the amplitude ramp signals I need, or is this overkill? Could I get away with a faster but cheaper DAC? Is using the laser signal in the above picture as a phase reference still possible? From my understanding, the answer is yes, but I want to make sure I am not missing anything.

Children
  • Hi,

    When you say ramp at 250MHz, do you mean the modulation frequency or carrier frequency?  Hi Jules, do you have a comment about this query?

    About the reference frequency from the laser,
    It depends on the quality of the reference. Normally PLLs require very clean reference signals to generate a clean output frequency. 

    Normally, Clock recovery circuits or jitter cleaner circuits are used to clean the reference. 

    If the phase noise of the signal is not important, you can use the signal from the laser as a reference to PLL. 

    Thanks,
    Emrecan

  • The ramps I want to generate are just the shape of the waveform, i.e. amplitude ramp with a repetition rate of 250 MHz. If I were to measure it on an oscilloscope, I would see a ramp signal. 

    The reference signal from the laser has about 2-5 ps of jitter. Since it is made of many harmonics, we were thinking about isolating one of them around 76 MHz or 158 MHz using a bandpass filter and using that as our reference. Our though is that the jitter is coming from the many harmonics which make up the pulses and, if we isolate one, the jitter should go away or at least be much less than 2 ps.