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Trying to control ADF 4356 Eval Board with Arty A7 FPGA Board

Category: Hardware
Product Number: ADF4356

Attempting to control ADF 4356 with my FPGA board.

Implemented a custom SPI master in the FPGA, clk frequency set at 10 MHz. Obtained the Register values from the ADI's software which comes with the eval board   

Connected the clk, data and LE test points on the eval board with GPIO from Arty A-7 board through jumpers with a resistor in between.

Observed that the CE pin stays always high after power is given hence no need to give it from FPGA.

 After programming, the current consumed by the board increases but No frequency is getting generated.

Attaching schematic of the Eval board. Encircled in red are points where I am giving input (coming from the FPGA )   



Also attached snapshots of my output waveform from the verilog code. 

Pl let me know possible causes of error, or is there something fundamentally wrong with my approach

Parents
  • Hi  ,

    Can you get output from the MUXOUT? You can get DVDD, GND, digital lock detection, and R divider output to see the PFD frequency. This can show if your SPI communication is OK and no issue between the Reference input pin and the REF source.  If you don't have a problem with communication then the registers should be checked. Also, are you using the CN1 and CN2 connectors? You can see we have series resistors before this connector's pins, if you bypassed the series resistors that might cause connection problems. These resistors also limit the SPI limit a bit. 

    Regards,
    Burhan

  • Hi Burhan, 

    So i checked by changing the muxout from dvdd to gnd and there is no change in the Output ,so i guess the SPI is not communicating properly, what can i do about it? as in what can be possible causes of failures in this. 

    I am not using the CN1 connectors but I have soldered a similar resistor in the jumper which goes from my FPGA to the eval board. Also can u pl tell me about  their relation with the SPI

    Many Thanks , 

    Deep

  • Hi  ,

    These resistors limit some overshoots which can cause problems at detecting the rising or falling edge. 1.5k is quite high, above 33 ohms is OK in general. you can replace them with 50 ohms because also they act as RC filters, which might suppress your SPI speed. 50 ohms may work better. CE pin can remain high to keep the chip in power-up. Are there any big decoupling capacitors on SPI lines to GND?

    Regards,
    Burhan

  • Hi Burhan,

    1) No there are no decoupling capacitors to GND on the SPI Lines, are they required ??

    2)  Just reconfirming , The eval board schematic uses a 1.5k resistor, but I should replace the one soldered on my jumper with a 50 ohms resistor?   

    Really appreciate your help with this.  

    Regards, 

    Deep 

  • Hi  ,

    1) It is not necessary. When there are some big caps on lines, it narrows the RC filters' pass band and may cause a problem.
    2) Yes, 1.5k is also OK, but it works well with the MCU on the EVAL board. For the FPGA, extending the RC filter passband may help. Do you use 3.3VDC or 1.8VDC as the logic level? ADF4356 works with 3.3VDC and ı can suggest checking this also with the FPGA output level. 

    Regards,
    Burhan

  • Hi Burhan, 
    Tried it with 50 ohm resistors, after I start the FPGA board the current drawn by the eval board goes down from 180 mA (default) to 66 mA, however no RF output is observed even after waiting for some time. 

    Yes i am working with 3.3 V logic level, have reconfirmed that as well.

    Basically approach wise can we conclude there is some electrical disturbance which is preventing the SPI lines from reaching the eval board??


    Please advise what can we check next
    Regards, 

    Deep

Reply
  • Hi Burhan, 
    Tried it with 50 ohm resistors, after I start the FPGA board the current drawn by the eval board goes down from 180 mA (default) to 66 mA, however no RF output is observed even after waiting for some time. 

    Yes i am working with 3.3 V logic level, have reconfirmed that as well.

    Basically approach wise can we conclude there is some electrical disturbance which is preventing the SPI lines from reaching the eval board??


    Please advise what can we check next
    Regards, 

    Deep

Children
  • Hi  ,

    It looks device is still not controlled by the SPI. Did you check the CE and LE pins? you mentioned that CE is always high so it is OK.
    you can check the guide below to debug the PLL. You can focus on the SPI timings and if there is any spur, spark, or noise.
    About the resistors, ı see 1.5k resistors from SPI lines to GND, do they still on the board? have you replaced the resistor between EVAL and the A7 board? my suggestion is: to remove the 1.5k resistors that go to ground, replace the resistors between EVAL and the FPGA boards with 50 ohms.

    How to Design and Debug a Phase-Locked Loop (PLL) Circuit | Analog Devices

    Regards,
    Burhan

  • Hi Burhan, 

    Resistors b/w FPGA and eval are 50 ohms. Removed the 1.5k resistors that go to ground. Now current input by eval board is significantly increased (from ~ 250 mA to ~490 mA). Also it is not even generating the default frequency which the eval generates before the FPGA gives it data. 

    Hope that the eval board has not been damaged by this change??

    Have gone through the guide and the part about SPI timing mostly seems covered.

    Please suggest what I can do next.

    Regards,

    Deep  

  • Hi   ,

    I would like to ask to be sure: R12, R13, and R14 are removed and not populated, and there are 50 ohm series resistors between the SPI pins and the FPGA board, right?
    These 1.5k resistors protect the SPI pins from floating conditions, so these pins will be in a low state. Removing these resistors would not cause a current increase, but if they were replaced with 50 ohms, it may. That would affect the FPGA board, not the ADF4356 board, but I think it is OK.
     One possibility is that the chip is already damaged and cannot communicate due to ESD, supply problems, short circuits, etc. Do you have a loose part to replace and control? You can measure the current chip's pin impedances with a multimeter. For example, the DATA and CLK pins are high impedance. You can see 5k ohm between REFINA and REFINB. These pins are also high impedance to the ground. 



    Regards,
    Burhan

  • Hi Burhan, 

    Yes my circuit is as per the drawing and yes the R12,R13,R14 are not present. One change is that there is a 50 Ohm on the CE line also (dont think that should be a problem). However current consumption has definitely shot up and the default VCO freq is also not observed. 
     
    The chip is not damaged because I was parallelly testing it with the Original Software and the SDP Shield and it was working before I removed the R12,R13 and R14. It is not working now. Should i refit the R12 ,R13 and R14??

    Regards,

    Deep

  • Hi Burhan,

    Update- added the R12,R13,R14 again. 
    The board is still taking much higher than normal current and not responding to software. I observed that the VDD , the 5 V and all other testpoints are also giving higher than normal voltage readings.


    1) Could the HMC 1060 voltage regulator be at fault?  

    2) If yes, what can be a replacement  ? (HMC 1060 is discontinued as per  ADI )

    3) Could there be any other reasons for this short -like behaviour? (Passive components look OK)

    Request you to kindly help out as best as you can. 

    Thanks, 

    Deep