Attempting to control ADF 4356 with my FPGA board.
Implemented a custom SPI master in the FPGA, clk frequency set at 10 MHz. Obtained the Register values from the ADI's software which comes with the eval board
Connected the clk, data and LE test points on the eval board with GPIO from Arty A-7 board through jumpers with a resistor in between.
Observed that the CE pin stays always high after power is given hence no need to give it from FPGA.
After programming, the current consumed by the board increases but No frequency is getting generated.
Attaching schematic of the Eval board. Encircled in red are points where I am giving input (coming from the FPGA )
Also attached snapshots of my output waveform from the verilog code.
Pl let me know possible causes of error, or is there something fundamentally wrong with my approach