Hi ADI
How important is it that the ADC_CLK is 100kHz for the ADF4371? What are the acceptable bounds? The datasheet says "Target 100 kHz for ADC_CLK". In the temperature measurement section of AN-2005 it says "Target 100 kHz for ADC_CLK and calculate ADC_CLK_DIV with the following equation....", it goes on to give an equation for making the ADC_CLK equal to 100kHz based upon the fPFD and adjusting ADC_CLK_DIV accordingly. The max value for ADC_CLK_DIV is 255 and AN-2005 says "If (the calculated value of) ADC_CLK_DIV is greater than 255, set it to 255". However the fPFD frequency may be up to 250MHz so the ADC_CLK may be up to 244kHz, is this acceptable? What is the lower bound? Is the lower bound only limited by how long you are prepared to wait before you take a temperature reading?
I assume the ADC is used when autocalibrating the VCO, does this have a bearing on the ADC_CLK frequency limits?
On a slightly different topic, I assume that when I have corectly calibrated the VCO, as per AN-2005, that when locked the VTUNE voltage is about half VCC. I would like to use the ADC to measure the VTUNE voltage to give me confidence that the VCO suitably calibrated. How do I do so? The datasheet gives hints that this is possible using ADC_MUX_SEL set to one. What else is required? What is the resulting scaling mentioned in the datasheet?
Thanks
JP
