Loop filter for HMC3716/HMC394

Hi Obabrin,

Your active loop-filter should output a DC voltage to drive your VCO. From your last screenshot, the yellow VTUNE voltage (Loop-filter output) does not tally with what is expected, although the Green waveform is correct. Also, it looks like you are operating out of range for you Op-AMP. I saw at room temperature +/-15V, is there a reason for this?

Some recommendations when designing your loop filter:
1. Ensure your loop bandwidth is less than 1/10th of your PFD frequency
2. Also ensure that your gain-bandwidth of 10x greater than the loop bandwidth

On your V- of your Op amp can be grounded to 0v while your V+ is kept at 15v room temperature. Make sure your VCO can handle your VTUNE range.

Regards

Hi obabarin ,

I could not find your reply for the notification I received. I hope you have resolved this now.

Regards,

Jude

Hi JudeOsems ,

The reply was deleted as I am now being stressed by this minor circuit. Which is why you did not see it. I do not have an explanation for why the loop filter behaves as reported.

I thought I had blown the op-amp circuit I was using in my setup, thinking I provided it with excess Vs but a fresh copy of the loop filter PCB that I made performs exactly the same way. And on this fresh copy, I ensured that the +Vs is +15V and -VS is GND.

I was also contemplating on making new loop filter PCBs, but that may not be reasonable as I have not figured out what is wrong and what corrections I am trying to implement.

Are there any guidelines on implementing the loop filter on a PCB? I was using the FR4 substrate, and I ensured that my traces are 50-Ohm. Any other suggestions? Also, is/are there any checks to perform on a loop filter to check its functionality?

Hi JudeOsems ,

The reply was deleted as I am now being stressed by this minor circuit. Which is why you did not see it. I do not have an explanation for why the loop filter behaves as reported.

I thought I had blown the op-amp circuit I was using in my setup, thinking I provided it with excess Vs but a fresh copy of the loop filter PCB that I made performs exactly the same way. And on this fresh copy, I ensured that the +Vs is +15V and -VS is GND.

I was also contemplating on making new loop filter PCBs, but that may not be reasonable as I have not figured out what is wrong and what corrections I am trying to implement.

Are there any guidelines on implementing the loop filter on a PCB? I was using the FR4 substrate, and I ensured that my traces are 50-Ohm. Any other suggestions? Also, is/are there any checks to perform on a loop filter to check its functionality?

Hiobabarin ,

I would assume that you had simulated your configuration, which is usually the first suggestion we give, to make sure you have the right components for setup. 

obabarin said:

Are there any guidelines on implementing the loop filter on a PCB?

The few guidelines when designing your loop filter PCB are:
1. Try to stick to high quality capacitors like C0G/NP0 capacitors to maintain performance.
2. You should only use low noise power supply to your loop filter.
3. The capacitors connected directly to your NU/ND output and to your VTUNE signals should be as close as possible to minimize trace length, reduce noise pickups, and prevent degradation of your signals.

4. For grounding, insert vias in ground pads of shunt caps so you are optimizing your ground connections.

5. Ensure you have proper thermal dissipation for your active components, as high temperatures can lead to drift in the values of your components. 

obabarin said:

Also, is/are there any checks to perform on a loop filter to check its functionality?

On this, if your design matches what you have simulated, there is no absolute reason why you should not get a DC Vtune voltage from your loop filter. There isn't any specific checks on the physical components that we do. 

Thanks for the answers. 

I was sure to simulate correctly and the target was loop bandwidth of 5MHz. I had previously simulated and fabricated the filter using LT1028 andLT6200 op-amps. Attached file is another simulation where I am exploring the ADA4625. 

I see that the parameters of the filters do not really change irrespective of the op-amp. But the voltage noise especially impact the total phase noise of the PLL.

To get realistic values for the Rs and Cs, I generated those from Tools->Build and that gave more realistic components values.

The PCB of the loop filter is powered from the TPS7A4701 LDO. And I mostly kept to other recommendations you gave. The caps I used are of X7R type though.

JudeOsems said:

3. The capacitors connected directly to your NU/ND output and to your VTUNE signals should be as close as possible to minimize trace length, reduce noise pickups, and prevent degradation of your signals.

To where should these caps to be close to? To the op-amp?

LO_SubHarmonicMixer_CustomAmp_960MHz_opamp_ADA4625_pfd_HMC3716.rar

Hi obabarin ,

Everything looks fine on your SIM file. You should ensure your NU/ND outputs are connected correctly to the Op-Amp. Also try to invert your PFD using your (INV - pin 3). If this does not resolve your issue, you could reduce your Loop bandwidth to 1MHz. For now, keep you V+/V- of your VCO at 0 to GND and +15V until you are able to produce a valid VTUNE and lock your part at a given frequency, you can then go ahead and apply negative voltage to cover your target lower frequency.

obabarin said:

To where should these caps to be close to? To the op-amp?

The caps on the PFD output should be as close to your NU/ND pins as possible and the caps on your VTUNE trace should be close to your VCO input as well.

Jude

Hi JudeOsems ,

I was away trying to solve for this problem. Sad to report that my problem persists, and I really need solutions. I made new copies of the PCB for the loop filter and incorporated the suggestions you gave. Using the ADISimPLL, I chose component values for three LBWs at approximately 5MHz, 1MHz and 500kHz. Unfortunately, all PCBs at this different LBWs performed in the same manner – which is super weird given that I have different values for the pre- and post- filters in these loop filter PCBs.

The screenshots from my oscilloscope are as follows with the green trace being input at the inverting pin of the op-amp, and the yellow trace being output of the loop filter:

1. LBW=500kHz loop filter

2. LBW=1MHz loop filter

3. LBW=5MHz loop filter

Then I dug further into understanding the topology of the loop filter, and I came up with chart below and I deduced that there is a pre-filter which has the topology of a 2-pole, 3^rd-order loop filter, but feeds the non-inverting input of the op-amp. And then a post-filter, which is simply a low pass RC filter, and the gain stage set by the non-inverting amplifier with gain defined by R1 and R2 while C2 acts as DC blocking on the negative feedback path.

Is my interpretation of the schematic given in ADISimPLL correct for this ‘active’ loop filter?

To troubleshoot my loop filter, I performed the follow tests: where I added test points at -IN and +IN inputs, OUT, and at points indicated in the diagram below:

TPT1 is at output of the loop filter before the post filter

TPT2 is at the DC blocking capacitor at the feedback path

TPT3 is at the input to the inverting pin of the op-amp

TPT4 is at the input to the non-inverting pin of the op-amp

Setup as follows:

REF = 160MHz; CLK = 960MHz, offset at 30Hz; N-divider = /6; +Vs = 10 or 12V, -Vs = GND;

My measurements data are follows:

1. C1 (yellow trace) at -IN; C2 (green trace) at TPT1; C3 (brown trace) at OUT:

Observed that signal at TPT1 and OUT are equal. Which doesn’t look correct to me as that will mean that the post-filter either as no effect on the signal or the frequency of signal is below the cut-off frequency of the signal.

2. C1 (yellow trace) at -IN; C2 (green trace) at TPT2; C3 (brown trace) at OUT:

Observed here that the trace at the input (-IN) and at the test point TPT2 (DC blocking cap) aligns. This is unexpected, but understood that the signal voltage here will be the same as the -IN given the resistor R2.

3. C1 (yellow trace) at -IN; C2 (green trace) at TPT3; C3 (brown trace) at OUT:

Observed here also that traces at -IN and TPT3 aligns. Not sure what to expect here.

4. C1 (yellow trace) at -IN; C2 (green trace) at TPT4; C3 (brown trace) at OUT:

Observed that the trace at TPT4 has DC value of +5V, which is much as expected as the +IN input is also +5V from NU of the PFD chip.

NB – I tried inverting/swapping NU and ND inputs, that only inverted the polarity of my traces, and no improvements than when NU and ND were not swapped.

What could I have been missing in the implementation of this loop filter on my PCB that is the problem? I just don’t seem to understand why I am having these troubles. Kindly take a look at Gerber files of my PCB in attachment also. Thanks very much for the supports.

obabarin_loopfilter_gerber.rar

Issues being documented/reported here may not be related to the loop filter. I will be updating these posts in the coming days on improvements made.