Can't generate wavefoorm with ADF415

Hi Raz,

I think we need to make sure that SPI communication is established with ADF4159. Can you probe the Muxout of the ADF4159?

If you consult this EZ post the reply includes a presentation about general PLL debug, you could work through this and see if it helps.

https://ez.analog.com/rf/f/q-a/71750/ev-adf4002sd1z-issues-with-programming/180197#180197

Thanks,

Emrecan

Hey! Thank you for your reply.

I'm not sure how to read MUXOUT, logic wise.
If I understand correctly, I should program the MUXOUT function in R0, but before writing to R0, I need to write to R7 down to R1, right?

And then what?
Can I read MUXOUT with a logic analyzer, or should I read it only with oscilloscope?
Also, what is the reading "command" (or logic?)? I know I need to generate a clock (using HAL_SPI_Receive? maybe Transmit?). Should I write address bit and then read? Should I only toggle LE to "1"? Should I pulse (toggle to 1 then to 0) the TXData GPIO?

I'm really not sure how the reading of MUXOUT works, and the datasheet wasn't really helpful for me :(

The PowerPoint presentation didn't help me with that as well, unfortunately.

Raz.

Hi Raz, 

You don't need to write all registers to change the muxout. you can set the MUXOUT bitfield at the register 0 to 1 and 2 respectively and observe pin 17 of the ADF4159. 

If SPI communication is established, Pin 17 of the ADF4159 should change its voltage depending on the Register 0 DB27 - DB30 bits. 

You can read the voltage level at pin 17 of the ADF4159 with a multimeter or oscilloscope. 

There is no need for a serial read at this point. We need to be sure that we can communicate with the chip first. 

Thanks,

Emrecan

Thank you so much for the explanation!

I have set R0 MUXOUT to DVdd and measure "1" at pin 17, then set it to DGND and measure "0".
So as much as I understand, SPI communication is established as expected.

what's next? :)

Hi Raz, 

After ensuring SPI is established, you need to debug the R Divider output and N divider output from the MUXOUT pin. This tells us that Reference and VCO are present. You can change the MUXOUT behavior and use an oscilloscope to measure pin 17 of the ADF4159. 

After ensuring both reference and VCO are present, the next step is measuring the VTune voltage with ramping disabled. By measuring the voltage at the input of the VCO, it is possible to determine if the part is close to a lock condition.

Achieving a lock with a ramping disabled is an important milestone. After that, we can investigate the loop filter and ramp configurations.

Another point I would like to bring that VCO frequency. Your register configured for 5.8Ghz RF input.  You said you are using Silicon Radar Easy R4. What is the frequency of the Div_o output of the Transceiver? N divider value should be set accordingly. 

Thanks,
Emrecan

Hi!
I'm not 100% sure about the flow of the programming.

I wrote to the R0 register 0x08000000 and then 0x10000000 to test DVdd and DGND, as you suggested.

So now I just need to keep this logic and write 0x18000000 and 0x20000000 for the R and N dividers, or should I first send all my custom settings and then modify the MUXOUT?

For now, I have just modified the MUXOUT, with no other settings (0x18000000, 0x20000000) and got this signal on pin 17 (same for both R and N dividers):

here is the write flow:

	void spi_write(uint32_t value) {
		uint8_t data_tx[4] = {0, 0, 0, 0};// TX SPI Buffer

		data_tx[0] = (uint8_t)((value & 0xFF000000) >> 24);
		data_tx[1] = (uint8_t)((value & 0x00FF0000) >> 16);
		data_tx[2] = (uint8_t)((value & 0x0000FF00) >> 8);
		data_tx[3] = (uint8_t)((value & 0x000000FF) >> 0);

		// WRITE
		HAL_GPIO_WritePin(PLL_LE_GPIO_Port, PLL_LE_Pin, GPIO_PIN_RESET);
//		HAL_Delay(1);
		HAL_SPI_Transmit(&hspi2, &data_tx, 4, 0);
		HAL_Delay(1);
		HAL_GPIO_WritePin(PLL_LE_GPIO_Port, PLL_LE_Pin, GPIO_PIN_SET);
		HAL_Delay(1);
		}
		

	// FRAC/INT (R0)
	data_tx = 0xFFFFFFFF & 0x08000000; // MUX_CONT = 1 (DVdd)
	spi_write(data_tx);

	// FRAC/INT (R0)
	data_tx = 0xFFFFFFFF & 0x10000000; // MUX_CONT = 2 (DGND)
	spi_write(data_tx);

	// FRAC/INT (R0)
	data_tx = 0xFFFFFFFF & 0x18000000; // MUX_CONT = 2 (R DIV)
	spi_write(data_tx);

	// FRAC/INT (R0)
	data_tx = 0xFFFFFFFF & 0x20000000; // MUX_CONT = 2 (N DIV)
	spi_write(data_tx);

Hi Raz, 

Now we established that we can communicate with the chip and reference is present. 

I am not familiar with Silicon Radar Easy R4. According to the schematic of the 24 GHz transceiver chip, divided output of the 24GHz are supplied to ADF4159 and divider value is 32. 

This means that your configuration to 5.8 GHz is not correct. Feedback to the ADF4159 is 750 MHz. So we need to set the R and N counter values accordingly. 

Can you use the below registers: 

I recommend disabling the ramp first and then measuring the Pin 17 and CP test points of the board. Once the lock is acquired, I recommend enabling the ramp and measuring the Vtune voltage at the CP test point of the board. 

Thanks,

Emrecan

Thank you very much for all the help up to this point, Emrecan!

Unfortunately, I won't be able to test it in the coming week but will get back to it right after and will update here!

In the meantime, could you briefly elaborate on how you calculated the divider value of 32 and the feedback of 750MHz?

I'm very new to the RF engineering field and might lack some basic knowledge at this point (which I surely going to change).

Thanks, again, Raz :)

Hi

I looked at the datasheet of the TRX_024_046. 

Here is the datasheet: 24 GHz Transceiver TRX_024_046 - indie Semiconductor FFO GmbH (siliconradar.com)

Then, I checked the block diagram of the part and saw the divider on the path that connected to ADF4159. 

Div_o output has a div-by-32 block.
 

This part works on the 24GHz band. So feedback to PLL should be TX frequency / 32. I set the R counter and N counter values according to Tx Frequency / 32 = 750MHz.

Then, I calculate the ramp parameters. As the ISM band allows for a 250MHz FMCW ramp, ADF4159 should provide 7.8125MHz ramp bandwidth for the chip. (250 / 32  = 7.8125)

You can model the ramp parameters in ADIsimPLL. I didn't want to change your ramp timings but ramp timing (ramp duration and ramp rate) can be improved. 

Link to tutorial: https://www.analog.com/en/resources/media-center/videos/1846356091001.html

Waiting for the good news :)

Regards,

Emrecan

Hi

I looked at the datasheet of the TRX_024_046. 

Here is the datasheet: 24 GHz Transceiver TRX_024_046 - indie Semiconductor FFO GmbH (siliconradar.com)

Then, I checked the block diagram of the part and saw the divider on the path that connected to ADF4159. 

Div_o output has a div-by-32 block.
 

This part works on the 24GHz band. So feedback to PLL should be TX frequency / 32. I set the R counter and N counter values according to Tx Frequency / 32 = 750MHz.

Then, I calculate the ramp parameters. As the ISM band allows for a 250MHz FMCW ramp, ADF4159 should provide 7.8125MHz ramp bandwidth for the chip. (250 / 32  = 7.8125)

You can model the ramp parameters in ADIsimPLL. I didn't want to change your ramp timings but ramp timing (ramp duration and ramp rate) can be improved. 

Link to tutorial: https://www.analog.com/en/resources/media-center/videos/1846356091001.html

Waiting for the good news :)

Regards,

Emrecan

Well, that makes a lot of sense (:

Your explanation was great! I will try to implement your recommendations as soon as possible and will update on the progress.