I have ADF4351X EVAL Board 2020_1_v1.4 and i want to make FPGA driver for it, in verilog i made an SPI Module for communication with ADF4350 using DATA , SCK , LE and CE Chip as per timing diagram given in the datasheet, from SDK i am sending each register from REG_5 to REG_0 through axi_GPIO. the range of VCO is 2200 MHz to 4400 MHz.
I am loading Registers in this sequency:
REG_5 ,
REG_4 ,
REG_3 ,
REG_2 ,
REG_1,
REG_0
Below are the values of registers(decimal) and SPI communication:
REG_0 = 57671680
REG_1 = 65529
REG_2 = 419598146
REG_3 = 1203
REG_4 = 8393788
REG_5 = 5767173
parameters:
REFin = 25MHz;
INT = 1760;
FRAC = 0;
MOD = 4095;
ref_doubler = 0;
ref_divider = 1;
R_counter =10;
R_divider =1;
This is my output on Spectrum Analyzer:
as the Output is 2200 MHz and when i change the INT value it can varry from 2200 MHz to 4400 MHz.
Now the problem is ADF4350 has output frquency range of 137.5 MHz to 4400 MHz, so we can use R-divider to achieve 137.5 MHz, R-divider has value 1,2,4,8 and 16, so when i turn on the divider and give any of these value.. the output frequency did not response to it and remain same. I want to know if there is any setting i am missing to work the divider properly so that i can achieve output frequency from 137.5 MHz to 4400 Mhz?