LO Phase Noise performance vs reference clock phase noise

Hello Guangyi,

First, before getting into the details of phase noise, I have a couple of comments about this MAX2851 part specifically.  I have reviewed the datasheet.  I can see no mention of supporting an 80MHz crystal.  The datasheet only mentions using a 40MHz crystal.  All specs in the electrical characteristics table are measured using a 40MHz crystal.  The spec for the reference clock frequency is stated as 40MHz typical - no min or max value.  I also read the datasheet for the MAX2851 EVKIT.  The EVKIT uses a 40MHz crystal (made by Kyocera but which is now obsolete).  There is no mention of a reference clock divider in the MAX2851 IC datasheet.  I see that the EVKIT datasheet shows a screen shot of the EVKIT GUI which seems to indicate a reference clock divider is present.  However, the EVKIT software is no longer available so I could not look at this.  The fact that the IC data sheet does not mention a refclk divider makes me think that it may exist but was hidden (made reserved).  Overall, I would say it may be risky to use an 80MHz crystal and it is recommended to use a 40MHz crystal.  

As for your questions on the theory of phase noise:

The reference clock phase noise for some crystal or TCXO will be specified in units of power (dBc/Hz).  One adds various phase contributors to the overall PLL output phase noise (PN) as power, not voltage.  The reference clock PN is often a big contributor to the PLL PN within the closed-loop PLL bandwidth.  In the figure you included, it can be seen the reference PN (yellow trace) completely dominates the PLL PN at low frequencies.  The reference PN contribution to the PLL PN at the VCO output is shaped by the frequency transfer function of the PLL.  Often PLLs will include a reference clock divider.  (Although as discussed above, we effectively don't have a reference clock divider in this part).  Whenever a clock is divided, the phase noise on that clock is also divided by the same factor.  For example, if the refclk division ratio (R) was 2, the phase noise would be reduced by a factor of 2 or 20*log(0.5) =6dB.  Since R = 1 for this IC, the raw reference clock phase noise is not affected by R.  The PLL transfer function from the reference signal to the PLL output contains a scaling factor of N where N is the division ratio of the frequency divider in the feedback path of the PLL.  So if we denote the raw refclk PN as PN(ref), the contribution at the output of the PLL will be PN(ref) + 20log(N) + filter_attenuation_dB.  filter_attenuation_dB is the PLL closed loop transfer function which is a low-pass filter with bandwidth determined by the loop filter.  As an example, if at 100Hz offset frequency the PN of the refclk = -136 dBc/Hz, assume N = 66, and filter_attenuation_dB = 0 (since the loop bandwidth will typically be much higher than 100Hz), the refclk PN contribution at the output will be -136 + 20log(66) = -99.6 dBc/Hz.  This will then be added to all the other contributors to PN such as the phase-frequency detector, loop filter etc.

In the article snippet your provide, the refclk phase noise is lumped into the flicker noise.  In my experience, generally speaking, refclk phase noise is not included in PLL flicker noise.  Flicker noise is defined as due to components within the PLL itself such as the Phase-Frequency Detector, and not from an external source.  However, I suppose it is just semantics.  As far as how to add flicker and flat noise, one would add them as powers.  We are converting voltages to power via 20*log(x) and adding in the log domain.

Hello Guangyi,

First, before getting into the details of phase noise, I have a couple of comments about this MAX2851 part specifically.  I have reviewed the datasheet.  I can see no mention of supporting an 80MHz crystal.  The datasheet only mentions using a 40MHz crystal.  All specs in the electrical characteristics table are measured using a 40MHz crystal.  The spec for the reference clock frequency is stated as 40MHz typical - no min or max value.  I also read the datasheet for the MAX2851 EVKIT.  The EVKIT uses a 40MHz crystal (made by Kyocera but which is now obsolete).  There is no mention of a reference clock divider in the MAX2851 IC datasheet.  I see that the EVKIT datasheet shows a screen shot of the EVKIT GUI which seems to indicate a reference clock divider is present.  However, the EVKIT software is no longer available so I could not look at this.  The fact that the IC data sheet does not mention a refclk divider makes me think that it may exist but was hidden (made reserved).  Overall, I would say it may be risky to use an 80MHz crystal and it is recommended to use a 40MHz crystal.  

As for your questions on the theory of phase noise:

The reference clock phase noise for some crystal or TCXO will be specified in units of power (dBc/Hz).  One adds various phase contributors to the overall PLL output phase noise (PN) as power, not voltage.  The reference clock PN is often a big contributor to the PLL PN within the closed-loop PLL bandwidth.  In the figure you included, it can be seen the reference PN (yellow trace) completely dominates the PLL PN at low frequencies.  The reference PN contribution to the PLL PN at the VCO output is shaped by the frequency transfer function of the PLL.  Often PLLs will include a reference clock divider.  (Although as discussed above, we effectively don't have a reference clock divider in this part).  Whenever a clock is divided, the phase noise on that clock is also divided by the same factor.  For example, if the refclk division ratio (R) was 2, the phase noise would be reduced by a factor of 2 or 20*log(0.5) =6dB.  Since R = 1 for this IC, the raw reference clock phase noise is not affected by R.  The PLL transfer function from the reference signal to the PLL output contains a scaling factor of N where N is the division ratio of the frequency divider in the feedback path of the PLL.  So if we denote the raw refclk PN as PN(ref), the contribution at the output of the PLL will be PN(ref) + 20log(N) + filter_attenuation_dB.  filter_attenuation_dB is the PLL closed loop transfer function which is a low-pass filter with bandwidth determined by the loop filter.  As an example, if at 100Hz offset frequency the PN of the refclk = -136 dBc/Hz, assume N = 66, and filter_attenuation_dB = 0 (since the loop bandwidth will typically be much higher than 100Hz), the refclk PN contribution at the output will be -136 + 20log(66) = -99.6 dBc/Hz.  This will then be added to all the other contributors to PN such as the phase-frequency detector, loop filter etc.

In the article snippet your provide, the refclk phase noise is lumped into the flicker noise.  In my experience, generally speaking, refclk phase noise is not included in PLL flicker noise.  Flicker noise is defined as due to components within the PLL itself such as the Phase-Frequency Detector, and not from an external source.  However, I suppose it is just semantics.  As far as how to add flicker and flat noise, one would add them as powers.  We are converting voltages to power via 20*log(x) and adding in the log domain.