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ADAR1000 programming

Category: Hardware
Product Number: ADAR1000

I am confused with the documentation for the ADAR1000 chip.  I am controlling 4 ADAR1000s to execute sequences of beam-forming operations.  Since I am agile in both beam pointing angles and frequency, I need to re-phase the array rapidly.  I would like to understand which registers are double buffered and the correct sequence to output controls to ensure that the beams point in the correct direction, at the correct frequency, and at the correct time.

I have read everything I can in the EZ, Rev B of the Datasheet and the errata sheet.

Here are my questions:

  • Which registers are double buffered? (ones that I can load for the next operation while still using the current set). 
  • What are the steps to trigger switching the double buffered registers?
    • The LD_WRK_REGS (0x28) do I need to sequence these(2,1), or can I write a 3 to sequence both Rx and Tx at the same time?
    • Do I need to clear the LD_WRK_REGS (x28) or is it self-clearing?
    • Do I always need to have 5 SCLK edges before the switch?
    • Does the transition happen when the Rx_Load/Tx_Load signal triggers or after the 5 SCLK edges?
    • When Mem_Ctrl (0x38) is set to 0x20, does writing RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) with bit 7 set cause the memory to shift?  
    • When Mem_Ctrl (0x38) is set to 0x2C, what does having bit 7 of RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) set do?
    • When Mem_Ctrl (0x38) is set to 0x2C and having a sequence of operations loaded in memory, I assume triggering the Rx_Load and Tx_Load pins will step through the memory.  Do I still need 5 SCLK edges between steps?
    • Short of using an VNA is there a way to determine the current settings of the Phase shifter and attenuators for each channel (to confirm everything is synchronized)?
    • Is there a way to know which step of the sequence the memory controller is pointing to?