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ADAR1000 programming

Category: Hardware
Product Number: ADAR1000

I am confused with the documentation for the ADAR1000 chip.  I am controlling 4 ADAR1000s to execute sequences of beam-forming operations.  Since I am agile in both beam pointing angles and frequency, I need to re-phase the array rapidly.  I would like to understand which registers are double buffered and the correct sequence to output controls to ensure that the beams point in the correct direction, at the correct frequency, and at the correct time.

I have read everything I can in the EZ, Rev B of the Datasheet and the errata sheet.

Here are my questions:

  • Which registers are double buffered? (ones that I can load for the next operation while still using the current set). 
  • What are the steps to trigger switching the double buffered registers?
    • The LD_WRK_REGS (0x28) do I need to sequence these(2,1), or can I write a 3 to sequence both Rx and Tx at the same time?
    • Do I need to clear the LD_WRK_REGS (x28) or is it self-clearing?
    • Do I always need to have 5 SCLK edges before the switch?
    • Does the transition happen when the Rx_Load/Tx_Load signal triggers or after the 5 SCLK edges?
    • When Mem_Ctrl (0x38) is set to 0x20, does writing RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) with bit 7 set cause the memory to shift?  
    • When Mem_Ctrl (0x38) is set to 0x2C, what does having bit 7 of RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) set do?
    • When Mem_Ctrl (0x38) is set to 0x2C and having a sequence of operations loaded in memory, I assume triggering the Rx_Load and Tx_Load pins will step through the memory.  Do I still need 5 SCLK edges between steps?
    • Short of using an VNA is there a way to determine the current settings of the Phase shifter and attenuators for each channel (to confirm everything is synchronized)?
    • Is there a way to know which step of the sequence the memory controller is pointing to?
  • Please see answers to your questions.  Hopefully this clears everything up. 

    • Which registers are double buffered? (ones that I can load for the next operation while still using the current set)

    A. All the gain and phase (I and Q Vector Modulator) registers are double buffered: 0x10 to 0x27

    • What are the steps to trigger switching the double buffered registers? 

    A. A Tx_Load or Rx_Load is needed via the pins or Register 0x28

    • The LD_WRK_REGS (0x28) do I need to sequence these(2,1), or can I write a 3 to sequence both Rx and Tx at the same time?

    A. If updating the gain and phase registers, you can write a 0x3 to register 0x28.  If sequencing through the beam positions in RAM, write a 0x1 or 0x2, but NOT 0x3.  This can cause a data loading error from RAM.

    • Do I need to clear the LD_WRK_REGS (x28) or is it self-clearing?

    A. I think it is self-clearing.  I'll double-check next time I'm in the lab.

    • Do I always need to have 5 SCLK edges before the switch?

    A. You need at least 6 SCLK edges, but this is only when loading beam position data from RAM.

    • Does the transition happen when the Rx_Load/Tx_Load signal triggers or after the 5 SCLK edges?

    A. RAM data is loaded Rx_Load/Tx_Load signal, but 6 SCLK edges must occur prior to the load signal, or the fetch & load does not happen properly.

    • When Mem_Ctrl (0x38) is set to 0x20, does writing RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) with bit 7 set cause the memory to shift?  

    A.  This only asserts the BIAS_RAM_BYPASS bit.  This tells the part to source the bias data from the registers rather than the RAM.  Registers 0x39 and 0x3A have no effect on the bias data. 

    Edit/Addendum: with reg 0x38 set to 0x20, you have the BIAS_RAM_BYPASS set to Low, which instructs the part to source the gain and phase data from RAM.  However, you need to fetch & load a beam position from RAM.  You can do this by writing the desired beam position index to 0x39 and 0x3A, followed by 6 SCLK cycles and a Tx or Rx Load command. Note that this applies the desired beam position data to all four channels.  There is a way to pull data from different beam positions for all four channels.  All of this is described in the Single Memory Fetch section in the datasheet.

    • When Mem_Ctrl (0x38) is set to 0x2C, what does having bit 7 of RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) set do?

    A. This enables the Rx and Tx RAM sequencers.  If you are planning to sequencing through the RAM, use registers 0x4D through 0x50 to set start and stop beam positions of the sequence.  See Sequencing Through Memory Beam Positions in the datasheet.

    • When Mem_Ctrl (0x38) is set to 0x2C and having a sequence of operations loaded in memory, I assume triggering the Rx_Load and Tx_Load pins will step through the memory.  Do I still need 5 SCLK edges between steps?

    A. You will need at least 6 SCLK edges AND an Rx_Load or Tx_Load between steps. 

    • Short of using an VNA is there a way to determine the current settings of the Phase shifter and attenuators for each channel (to confirm everything is synchronized)?

    A.  Unfortunately, there is no way to read back the raw data that is applied to the gain and phase blocks. 

    • Is there a way to know which step of the sequence the memory controller is pointing to?

    A.  No, the active beam position index in not available to read back. 

  • Thank you for your prompt response!

    Follow-up questions: 

    What does bit 7 in RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) do?

    The Sequencing Through Memory Beam Positions in the datasheet leaves me a little confused.  My design is expecting to step through the memory for both transmit and receive.  Item 3 The has how to step through transmit and instructions for stepping through receive but not both.  There appears to be errata associated with the initial load of memory for the transmit beam position. Can you confirm if the following will work:

    • load phase and amplitude controls into memory
    • load memory control registers (0x4D,0x4E -- transmit) (0x4F and 0x50--Receive) to point to the memory
    • set Tx_Beam_Step_Enable in Mem_CTRL (0x38)
    • 6 clocks
    • send a Tx_Load strobe
    • set both Tx_Beam_Step_Enable and Rx_Beam_Step Enable in Mem_CTRL (0x38)
    • 6 clocks
    • Send Rx_Load strobe

    At this point I believe the ADARs should be ready to complete the first beamforming operation defined in memory... from this point on, I believe I can repeat the following to sequence through the operations pointed to in memory:

    •  6 clocks
    • Tx_load strobe
    • Rx_load strobe

    Since I need to artificially force 6 SCLK bus clocks anyways, I have considered using the RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) registers to pick the next beam position... plus I would not need to play with the tx_beam_step_enable and then Tx &  Rx_beam_step enable as described above. Again please confirm if you think this will work:

    • load phase and amplitude controls into memory

    Now sequencing would be:

    • write RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A) to point to the correct memory
    • 6 clocks
    • send a Tx_Load strobe
    • Send Rx_Load strobe

    The prior command will be active until the two strobes are sent.

  • Bit 7 in RX_CHX_MEM(0x39) and TX_CHX_MEM(0x3A), and Registers 0x3D to 0x44, is a data fetch bit.  It basically instructs the part that you are ready to fetch the beam position data in RAM indicate in 0x39 and 0x3A. 

    As far as beam position sequencing and Item 3 in Sequencing Through Memory Beam Positions, you can sequence through both Rx and Tx, you just cannot fetch & load the first Tx beam position properly while the Receive Sequencer is enabled (Rx_Beam_Step Enable = High).  This is a Silicon Error as you mentioned.

    The first sequence you wrote should load Tx and Rx beam position just fine.  The second sequence needs another group of SCLKs:

    • 6 clocks
    • Tx_load strobe
    • 6 clocks
    • Rx_load strobe

    In the last sequence you still need another set of 6 clocks between the Load strobes, so I don't know if that saves clock cycles.  And once you go through the first awkward sequence outlined in your first sequence, you do not have to do the de-assert/assert of the Rx_Beam_Step Enable bit.  On the 2nd time through the Tx sequence, the first Tx beam position loads without errors even with Rx_Beam_Step Enable bit asserted.