What is the level of reflected power the ADL5372 can tolerate at the Vout terminal without failure?
This is not a normal operating condition but a failure of a circuit downstream and need to understand the implications to the ADL5372 device.
Maximum operating conditions are +13dBm at the LOIP/LOIN interface but this is likely buffered by an amplifier and totally different form the output interface.
Will the output stage fail/degrade/survive?