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Is it OK to mix 4 wire SPI(ADF5902, ADF5904) with a 3 wire SPI interface of (ADF 4159).

Category: Hardware
Product Number: ADF 4159

In my custom board, We are planning to interface SPI 4 wire controller with 3 chip selects/latch enable for 3 different devices ADF5902, ADF 5904 and ADF 4159 ICs.

Here, PLL ADF4159 has SPI interface with a 3 wire (CLK, DATA_IN, LE) . However, VCO transmitter ADF5902 and Receiver ADF5904 have 4 wire SPI interface  (CLK, DATA_IN, LE, DATA_OUT) . Now due to lack of pins on output connector, I need to connect using common SPI controller with 3 devices with common Clk, DATA_IN, CE, DATA_OUT with 3 different LE (CS).
Now, Is it ok to mix 4 wire SPI (ADF5902 and ADF5904) with a 3 wire SPI interface of (ADF 4159)? Are there any other constraints I need to take care of ?
Regards,
SP
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  • Hi PSA1, 

    You can mix 3-wire SPI with 4-wire SPI communication as long as each chip has an individual chip select line. 

    I recommend placing a 30Ohm series resistance on the SPI lines to prevent peaking at the edges of the clock line and data line.  

    Thanks,

    Emrecan

  • Hi Emrecan,

    The datasheet for ADF4159 (Table 6) says for LE pin: "Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight latches;...". If LE is held high while writing to other devices on the SPI bus, can we unknowingly write the ADF4159 registers?

    Just to confirm, is ADF4159 input shift register data loaded  when LE is high, or when LE has a rising edge? 

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  • Hi Emrecan,

    The datasheet for ADF4159 (Table 6) says for LE pin: "Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight latches;...". If LE is held high while writing to other devices on the SPI bus, can we unknowingly write the ADF4159 registers?

    Just to confirm, is ADF4159 input shift register data loaded  when LE is high, or when LE has a rising edge? 

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