In my custom board, We are planning to interface SPI 4 wire controller with 3 chip selects/latch enable for 3 different devices ADF5902, ADF 5904 and ADF 4159 ICs.
ADF5902
Recommended for New Designs
The ADF5902 is a 24 GHz transmitter (Tx) monolithic microwave
integrated circuit (MMIC) with an on-chip, 24 GHz voltage
controlled oscillator (VCO). The...
Datasheet
ADF5902 on Analog.com
ADF4159
Recommended for New Designs
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer with modulation and both fast and slow waveform generation capability. The part uses a 25-bit...
Datasheet
ADF4159 on Analog.com
ADF5904
Recommended for New Designs
The ADF5904 is a 4-channel, 24 GHz, receiver downconverter.
Each channel contains a single-ended RF input with an on-chip
balun followed by a differential...
Datasheet
ADF5904 on Analog.com
In my custom board, We are planning to interface SPI 4 wire controller with 3 chip selects/latch enable for 3 different devices ADF5902, ADF 5904 and ADF 4159 ICs.
Hi PSA1,
You can mix 3-wire SPI with 4-wire SPI communication as long as each chip has an individual chip select line.
I recommend placing a 30Ohm series resistance on the SPI lines to prevent peaking at the edges of the clock line and data line.
Thanks,
Emrecan
Hi Emrecan,
The datasheet for ADF4159 (Table 6) says for LE pin: "Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight latches;...". If LE is held high while writing to other devices on the SPI bus, can we unknowingly write the ADF4159 registers?
Just to confirm, is ADF4159 input shift register data loaded when LE is high, or when LE has a rising edge?
Hi Emrecan,
The datasheet for ADF4159 (Table 6) says for LE pin: "Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight latches;...". If LE is held high while writing to other devices on the SPI bus, can we unknowingly write the ADF4159 registers?
Just to confirm, is ADF4159 input shift register data loaded when LE is high, or when LE has a rising edge?
Hi,
The data stored at the shift register is loaded when a rising edge of LE is detected. When LE is high, input buffers are insensitive to SPI line communication
Thanks,
Emrecan