| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. | MStokowski JudeOsems PeterW kieranb |
Open |
ADF4382A
Recommended for New Designs
The ADF4382A is a high performance, ultralow jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally...
Datasheet
ADF4382A on Analog.com
Hello,
I used ADISimPLL on the new ADF4382A MMIC.
In the simulation was able to use a FREF=5MHz with divider R=10 to get Fdet = 500 kHz.
However, in the data-sheet I see FREF(min)=10 MHz and Fdet(min)=5.4 MHz.
Can you confirm that there is a problem with the ADISimPLL model of the ADF4382A ? Or am I not reading the data-sheet correctly?
Thank you for your support and feedback!
stephenv - Moved from Other Products (EN) to RF & Microwave. Post date updated from Tuesday, March 19, 2024 11:50 AM UTC to Tuesday, February 3, 2026 9:08 PM UTC to reflect the move.
stephenv - Moved from Other Products (EN) to RF & Microwave. Post date updated from Tuesday, February 3, 2026 9:08 PM UTC to Tuesday, February 3, 2026 9:08 PM UTC to reflect the move.
Hi,
The datasheet is correct. The model in SimPLL will need to be changed to reflect this. Thanks for bringing this to our attention.
Regards,
Kieran