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ADF4377 with LTC6954 as a buffer

Category: Hardware
Product Number: LTC6954


First, thank you for the quality of your devices and the support you provide to all of us here.

I am creating a board whose aim is to generate a RF signal from 9.6GHz to 13.44GHz in 640MHz steps. My main goal is to have the lowest phase noise possible.

I also need a 40MHz reference out from that board.

My choice felt on the following items:
* 160MHz XO (Ultra low PN, -173dBc/Hz Noise floor, -140dBc/Hz @1kHz offset)
* LTC6954-3 as a buffer and divider to generate my 40MHz on a CMOS output
* ADF4377 for the final stage.

Between the buffer and the PLL I would follow the LTC6954 recommendation, since ADF4377 ref input is self biased and must be AC coupled.

But which capacitor is best ? one datasheet says 1uF, the other one 0.1uF ?
Second question, would you see an other setup/device choice that could improve the output phase noise further ?

Thank you for your help !


  • Hi Gael, 

    Either capacitor will work.  Originally, the 100nF was the recommended option.  At some point, we noticed the 1uF cap provided marginally better 1/f noise (very close in phase noise <1kHz).  Looks like we forgot to update every section of the datasheet to apply this best practice.  I'm not sure that the marginal improvement in most cases is noticeable.

    Your approach is a good solution to generate 40MHz and 9.6GHz.  LTC6954 has a low additive jitter compared to ADI's other buffers. And divider functionality allows to get divided output. 


  • Hello Emrecan,

    Thank you for you reply!

    Would you also recommend to use 1uF iso 0.1uF for the input interface ?

    Thank you

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