Hello!
First, thank you for the quality of your devices and the support you provide to all of us here.
I am creating a board whose aim is to generate a RF signal from 9.6GHz to 13.44GHz in 640MHz steps. My main goal is to have the lowest phase noise possible.
I also need a 40MHz reference out from that board.
My choice felt on the following items:
* 160MHz XO (Ultra low PN, -173dBc/Hz Noise floor, -140dBc/Hz @1kHz offset)
* LTC6954-3 as a buffer and divider to generate my 40MHz on a CMOS output
* ADF4377 for the final stage.
Between the buffer and the PLL I would follow the LTC6954 recommendation, since ADF4377 ref input is self biased and must be AC coupled.
But which capacitor is best ? one datasheet says 1uF, the other one 0.1uF ?
Second question, would you see an other setup/device choice that could improve the output phase noise further ?
Thank you for your help !
Gael
