ADF4368 Single Side phase noise issue

Question

Hi, ADI 
 There is no test result for 500MHz PFD and integer mode in ADF4368 datasheet. Is this same to ADF4377 with same normalized in-band phase noise floor and 1/f noise. ADF4368 Single Side phase noise at 12GHz f out and fPFD=500MHz is about -122dBc/Hz@10kHz and 100kHz like the screenshot below. But in my test，this spec only is about -116dBc/Hz@10kHz and 100kHz in my ADF4368 board. I think there is something wrong with it. could you share to me the test results for 500MHz PFD and integer mode in ADF4368 and register setting? By the way, The intput ref is a 100MHz Oscillator with -167dBc/Hz@100kHz. thank you very much!

emrecangidik · Accepted Answer

Hi Zopo1988, 
 The integer phase noise of ADF4368 with 500MHz PFD frequency is the same as ADF4377. ADF4368 and ADF4377 share the same PLL core with additional delay blocks. If these delay blocks are not enabled, the PLL performance of the ADF4377 is the same as the integer mode performance of the ADF4368. 
 
 I see you are using 100MHZ reference input. I recommend enabling the doubler at the input to achieve 200MHz PFD frequency. 
 I think you see this difference between 122dBc/Hz vs 116dBc/Hz because of the PFD frequency difference. 
 10kHz and 100kHz offsets mainly focused on the in-band noise region of the PLL. To calculate the in-band noise of the PLL, we can use the following formula 
 
 where Lnorm is the normalized in-band noise floor of the ADF4377 which is -239dBc/Hz. 
 For 100MHz PFD frequency, a minimum of -117.41dBc/Hz in-band noise floor can be achievable. 
 For 200MHz PFD frequency, a minimum of -120.42dBc/Hz in-band noise floor can be achievable. 
 For 500MHz PFD frequency, a minimum of -124.43dBc/Hz in-band noise floor can be achievable. 
 You may notice a pattern between calculations. From the calculation, we can extract that doubling the PFD frequency decreased the in-band noise of PLL by 3dB. 
 As you can see measuring -116dBc/Hz in-band noise is expected for ADF4377 or ADF4368 in integer mode when using 100MHz PFD frequency 
 There are additional noise contributors in the PLL system. Reference noise and loop filter noise are the noise contributors that can affect in-band noise measurements. You can model these noises and simulate our PLL/VCO products by using ADISimPLL software accessible on analog.com/adisimpll 
 Thanks, 
 Emrecan)

emrecangidik · Answer

Hi, 
 I understand now. Thanks for the clarification. 
 I have attached an ACE Plugin screenshot for 500MHz input and 500MHz PFD frequency.

What is your filter mechanism after the comb generator? Can you share a block diagram? Can you share the spectrum view and phase noise measurements for reference of ADF4368? 
 PLL references require clean input signals for better performance. Comb generators produce high-power harmonic contributors. You need to be sure that filtering is sufficient to have a clean 500MHz reference from the comb generator. 
 Thanks, 
 Emrecan

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ADF4368 Single Side phase noise issue