ADF4368 Single Side phase noise issue

Hi Zopo1988,

The integer phase noise of ADF4368 with 500MHz PFD frequency is the same as ADF4377. ADF4368 and ADF4377 share the same PLL core with additional delay blocks. If these delay blocks are not enabled, the PLL performance of the ADF4377 is the same as the integer mode performance of the ADF4368.

I see you are using 100MHZ reference input. I recommend enabling the doubler at the input to achieve 200MHz PFD frequency.  

I think you see this difference between 122dBc/Hz vs 116dBc/Hz because of the PFD frequency difference. 

10kHz and 100kHz offsets mainly focused on the in-band noise region of the PLL. To calculate the in-band noise of the PLL, we can use the following formula

where Lnorm is the normalized in-band noise floor of the ADF4377 which is -239dBc/Hz. 

For 100MHz PFD frequency, a minimum of -117.41dBc/Hz in-band noise floor can be achievable.

For 200MHz PFD frequency, a minimum of -120.42dBc/Hz in-band noise floor can be achievable.

For 500MHz PFD frequency, a minimum of -124.43dBc/Hz in-band noise floor can be achievable.

You may notice a pattern between calculations. From the calculation, we can extract that doubling the PFD frequency decreased the in-band noise of PLL by 3dB. 

As you can see measuring -116dBc/Hz in-band noise is expected for ADF4377 or ADF4368 in integer mode when using 100MHz PFD frequency 

There are additional noise contributors in the PLL system. Reference noise and loop filter noise are the noise contributors that can affect in-band noise measurements. You can model these noises and simulate our PLL/VCO products by using ADISimPLL software accessible on analog.com/adisimpll

Thanks,

Emrecan

Hi Emrecan,

Follow your suggestion, I use ADISimPLL software to simulate the Phase noise like the screenshot below. Simulation results is about -120dBc/Hz, having a big gap with my test results. Mybe I think there is something wrong with Register setting. Could you share it to me?  Thanks a lot.

Hi,

I understand now. Thanks for the clarification. 

I have attached an ACE Plugin screenshot for 500MHz input and 500MHz PFD frequency. 

What is your filter mechanism after the comb generator? Can you share a block diagram? Can you share the spectrum view and phase noise measurements for reference of ADF4368? 

PLL references require clean input signals for better performance. Comb generators produce high-power harmonic contributors. You need to be sure that filtering is sufficient to have a clean 500MHz reference from the comb generator. 

Thanks,

Emrecan

Hi,

I understand now. Thanks for the clarification. 

I have attached an ACE Plugin screenshot for 500MHz input and 500MHz PFD frequency. 

What is your filter mechanism after the comb generator? Can you share a block diagram? Can you share the spectrum view and phase noise measurements for reference of ADF4368? 

PLL references require clean input signals for better performance. Comb generators produce high-power harmonic contributors. You need to be sure that filtering is sufficient to have a clean 500MHz reference from the comb generator. 

Thanks,

Emrecan

Hi, Emrecan

Thank you for your timely reply!

The first screenshot below is the block diagram showing 500MHz generator in my board. After Comb generators, two narrow band saw filters are used to remove useless harmonics of 100MHz signal and an amplifer are used to amplify power bigger than 3dBm as reference of ADF4368.

The second screenshot below is the phase noise measurements for reference of ADF4368 at test point in  first screenshot. The measurements are -149.5dBc/Hz@10kHz and -151.5dBc/Hz@100kHz. Considering of the influence of reference, the theoretical value of phase noise for ADF4368 12GHz output should be about  -119dBc/Hz@10kHz and -120.5dBc/Hz@100kHz.

The third screenshot is the measurement phase noise of ADF4368 12GHz output, measurement is about -116dBc/Hz@10kHz and 100kHz. There is about 3-4dB gap with theoretical value. could you give out improvement suggestion?

Thank you very much!

BRs

zopo

Hi Zopo, 

Thanks for sharing the reference phase noise and block diagram. 

Your calculations are correct. a -120dBc/hz@100kHz offset is achievable with your reference signal. 

Upon investigating the screenshot of 12GHz phase noise measurements, I realized your loop filter behavior is not as expected.

Are you using a custom loop filter? if so, did you simulate your loop filter with ADISimPLL? 

the loop filter on the evaluation board is designed for 245.76MHz PFD frequency. I attached an ADISimPLL model with your reference noise/slew rate. You can investigate this simulation and compare it with your measurements and simulations. 

EZ_NLTL_COMB_500MHzPFD_0V7SlewRate.zip

Can you decrease the charge pump current to see if the loop filter cut-off frequency shifts to the left (Reducing the charge pump current decreases the loop filter bandwidth.)

Another probable reason for this behavior is the reference input power. The screenshot states input power is -8dBm, is that correct?

The slew rate affects the normalized in-band noise of the PLL. 

Slew Rate   = 2 × π × fREF × VPK = 2 x  π x 500MHz x 0.25 = ~0.7V/ns for sinusoidal signal.  ADF4368 can achieve a normalized in-band noise floor of -237.5 with 0.7V/ns. There is a 1.5db loss because of the slew rate. 

Figure 37 on the datasheet of ADF4377 gives a good comparison between slew rate vs Lnorm. 

To summarize, my suggestions would be:

• Checking loop filter performance by changing the charge pump current. 
• Improving the loop filter by designing a new loop filter for 500MHz PFD frequency
• Increasing the slew rate of the input signal. 

Thanks,

Emrecan