Hey all!
I'm presently trying to use the MAX2120 in a design; in spite of my best efforts, the status registers always report that the PLL is not locked, and that the VCO autoselection has failed.
I'm using an 8MHz clock into the 2120 and the following settings to trying and achieve an LO of 1090MHz:
- XTAL divide by 2
- VCO divide-by 2/4: 4
- R = 1
- N = 1090
The STATUS registers show the following, I believe indicating that VAS was attempted and failed.
- POR = 0
- VASA = 0
- VASE = 1
- LD = 0
- VCOSBR[4:0] = 0b11111
| Register | Value | Description |
| N_MSB | 0x04 | N=1090 MSB |
| N_LSB | 0x42 | N=1090 LSB |
| CHARGE_PUMP | 0x00 | Per datasheet must-set |
| N/A | 0x00 | No F-divider on 2120 |
| N/A | 0x00 | |
| XTAL_REF | 0x21 | XTAL divide-by 2, R=1 |
| PLL | 0xe0 | VCO divide-by 4, VAS charge-pump, 1200uA |
| VCO | 0xcc | VAS enabled, latch disabled, non-VAS tuning voltage ADC read disabled |
| LP_FILTER | 0x4b | Per datasheet default |
| CONTROL | 0x0f | Non-standby, baseband gain 15dB |
| SHUTDOWN | 0x00 | Nothing shutdown |
| TEST | 0x08 | Charge-pump fast lock (per datasheet must-set) |
| STATUS_1 | 0x21 | !POR, !VASA, VASE, !LD |
| STATUS_2 | 0xff | VCO band 11111, VAS ADC invalid because VCO register |
Given everything I see here, this should result in a lock. The REFOUT pin is displaying the 8MHz clock divided by 2 as expected, ending up at 4MHz, but the PLL is still marked as unlocked and the IQ data looks like just noise. What am I missing? What would get this design to properly lock? The datasheet is sparse on details for this particular IC so it's difficult to tell what VCO could be used in manual mode either. I appreciate anyone's help in getting this going!
