ADF4001Production
The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of...
Datasheet ADF4001 on Analog.com
when the REFIN is removed after 3 or 5 phase detector cycle ( 15ns each), the PLL loses the lock and the DLD should go to active high. Analog lock detect works in reverse.
I am sorry for the misinformation. This part's digital lock detection goes active high when the lock is detected. I explained in reverse at the above explanation. so when the PFD does not detect a high difference and detect the lock, you should see high voltage. when the REFIN is removed, the pfd detects a big phase difference and the internal circuit take the DLD output to low. pfd compares the REFIN to RFIN, when one of them is too low frew or too high freq ( actually N divider and R dividers output), there would be no lock.
I am sorry for the misinformation. This part's digital lock detection goes active high when the lock is detected. I explained in reverse at the above explanation. so when the PFD does not detect a high difference and detect the lock, you should see high voltage. when the REFIN is removed, the pfd detects a big phase difference and the internal circuit take the DLD output to low. pfd compares the REFIN to RFIN, when one of them is too low frew or too high freq ( actually N divider and R dividers output), there would be no lock.
