Unlock For RFin lower then 500MHz

Hi Roni,



Are you seeing a loss in the output power of your feedback frequency?
From the datasheet screenshot above, the ADF4150HV is characterized for frequency between 500MHz and 3GHz, to hit lower frequencies you will need to ensure that the slew rate is above 400V/us otherwise you will experience loss in VCO RFO (Based on your schematics) output power which can cause your PLL to unlock. If this is your case, you need to implement some coupler circuitry or amplifier on your feedback frequency to boost your slew rate as specified in the datasheet. 

I hope this helps.
Jude

Thanks Jude

I am familiar with datasheet. (the 400v/us)

Still, this PLL is locked at 400MHz to 450MHz. 
If it was power level issue than lower frequencies could be worse?

In addition, do you understand the reason to the bad phase noise (it occurs up to 510MHz of the vco frequency)

What do you mean by adding amplifier to the feedback, the vco power is 5dbm, should we amplify it? 
Regards

Roni

Hi Roni,

Commtact said:

Still, this PLL is locked at 400MHz to 450MHz. 

We cannot ascertain the behavior nor guarantee the performance of the PLL as you are operating at an out of specification range less than 500MHz. You can only get a reasonable output performance following my initial suggestion when you apply a square wave input frequency with slew rate above 400V/us. Here is a simple application of a case where you need to do the above CN0290 Circuit Note | Analog Devices

Commtact said:

If it was power level issue than lower frequencies could be worse?

Yes, because when you have a lower output frequency, there is a possibility that it will have a relatively low output power which would feed back as a reference point to close the loop, the mismatch in the output power with that of the reference would cause your PLL to unlock within the approximate 15ns window.

Commtact said:

In addition, do you understand the reason to the bad phase noise (it occurs up to 510MHz of the vco frequency)

I would try to replicate this in our lab to get more information. In the meantime, if you can provide your Reference Frequency, PFD frequency and a screenshot of your phase noise plot with the problem region, we can also use the ADISIMPLL to model your setup.

Regards,
Jude

Hi Roni,

Were you able to sort out your issue? Following up on my last reply, to replicate the poor phase noise issue you are seeing within the operating frequency range, it would be helpful if you can provide your reference frequency and PFD frequency, and maybe your phase noise plot to enable us better understand the issue.
Feel free to drop a reply as soon as you can.

Regards,
Jude 

Thanks, Jude, For the Replay
the Reference Frequency is 6.5MHz (26MHz/4)
For 480MHz (Bad phase noise) Ndivider=73, Frac=11, Mod=13
For 600MHz (Good phase noise) Ndivider=92, Frac=4, Mod=13
See attached the plots.
1st plot is 480MHz with bad phase noise. 
2nd plot is 600MHz with good phase noise.

Hi Commtact,

Based on our findings, this issues is most likely due to the PLL limitation for your out of specification range. If you can try my earlier advise to use a square wave as your Fref with higher Vp-p ( >= 1.6Vp-p) it may work in this case, although we can't fully guarantee this.

Regards,
Jude