ADF4368 Queries

Hi Manikandan_M_M ,

1- 3V3 supply groups can be combined. Placing an RF bead between LDO and different supply groups would be a good engineering practice.

2- A single-ended reference can be fed to ADF4368.  Page 22 of the datasheet shows different configurations for single-ended reference sources.

3- Your calculations are correct. Please ensure that amplitude at ADF4368 REFP input is <2.6Vpp if it is a square wave or <12dBm if it is a sinewave. A reference clock with a good slew rate is important for lower phase noise at the output. If the reference is a sine wave, the slew rate is directly correlated with frequency and amplitude. therefore using a higher peak-to-peak swing level at the input results in better performance.  

4- ADISimPLL is a good place to start for loop filter design and reference noise modeling. ADF4368 has an ACE plugin to communicate with evaluation software. ACE software can be used without an evaluation board. You can use the interactive user interface of ACE to calculate ADF4368 parameters.

ADISimPLL:  ADIsimPLL | Design Center | Analog Devices

ACE: Analysis | Control | Evaluation (ACE) Software | Design Center | Analog Devices

ADF4368 ACE Plugin:  EVAL-ADF4368 Evaluation Board | Analog Devices

5- Yes, SYNC input can be driven from LTC6953. It can be DC coupled. Below is the interface between LTC6953 and ADF4368 in our application boards.

6- LVDS is a current driving logic and needs a DC return path for proper operation. This DC return path is provided by 150Ohm resistors for the LVPECL logic. 

7- A small programmable constant charge pump current, known as bleed current (IBLEED), can be used to optimize the phase noise and fractional spurious signals in fractional mode. In ınteger mode, this bleed can be used to provide a phase shift at the output. 

8- it is a good practice to align reference signals if multiple ADF4368 is used. Although ADF4368 has phase shift capability (Page 25 of the Datasheet), this phase shift feature is limited and might compensate for reference mismatch.

Thanks,

Emrecan

Thanks for your reply emrecangidik

5th Point- LTC6952 Has common-mode voltage of 3.3-1 is 2.3V. But ADF4368 Self-bias voltage is 1.85V for CML standard. There is a common-mode mismatch?

How to do dc couple CML to LVDS for one-shot SYSREF. LTC6952 output is CML Logic. FPGA input is LVDS

How to choose Loop Bandwidth, less than pfd/10 or intersection of VCO and Ref noise?

Hi,

1.85V is the self-bias of the input when ADF4368's is AC coupled. ADF4368 input buffer can accept common voltage from 1.4V to 3.1V when DC coupling is used. So, using DC Coupled LTC6952 is suitable for ADF4368. 

Page 50 of LTC6953 datasheet give some example to DC couple between LTC6953 and FPGA. This is also valid for LTC6952. You can check the below thread for further information. 

Link: (+) LTC6952, LTC6953: SYSREF schematics when there is a common mode mis-match - Q&A - Clock and Timing - EngineerZone (analog.com)

You can use ADISimPLL to design a loop filter. There is option to model the reference noise and VCO noise. ADF4368 is fully modeled. You can see noise contribution of each component and design the loop filter accordingly.

Thanks,

Emrecan

Thanks for the reply.

I am unable to find the input common mode voltage range of ADF4368 for SYNCP/N.  could you please share that doc?

Hi,

ADF4368 has input common-mode voltage ranges of 1.4 to 3.1V when SYNC_SEL = 0 (CML Mode)

And ADF4368 has input common mode voltage range of 0.5 to 1.6V when SYNC_SEL = 1 (LVDS)

Thanks,

Emrecan