Category: Datasheet/Specs
Product Number: HMC783
I wanted to perform an experiment with an existing design where I increase the internal PFD of the HMC783 chip. For this configuration I would be using a reference and PFD of 101 MHz. In looking at the datasheet both of these should be acceptable (reference max = 200 MHz, PFD max in integer mode = 140 MHz). When I try to create a new model in SimPLL I get an error that states "HMC783 is incompatible with these requirements: PLL Phase Detector frequency too high for HMC783" I understand this PFD would be too high for a fractional design but I am curious as to why SimPLL is preventing me from moving forward with my integer configuration. Any insight is appreciated.