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ADL5206 Parallel 5-bit control interface with latch - Cannot find timing diagram

Category: Datasheet/Specs
Product Number: ADL5206


The ADL5206 talks about the Parallel 5-bit control interface with latch. However, I cannot find any timing diagram for it. 

Where can I find the timing diagram? How fast can I run the parallel interface? 



Thread Notes

DylanM - Moved from ADC Drivers to Amplifiers. Post date updated from Friday, December 1, 2023 to Friday, December 1, 2023 to reflect the move.

GLADION - Moved from Amplifiers to RF and Microwave. Post date updated from Friday, December 1, 2023 to Saturday, December 2, 2023 to reflect the move.

  • Hi,

    To configure the part in parallel high-performance mode, MODE1 and MODE0 should be 0 as discussed in the digital interface overview section of the datasheet. In parallel usage, the LATCH pin could either be set to low which puts the part in transparent mode or set to high (and pulsed down) to operate the part in latched mode. You can run the parallel interface with 25MHz rate and the gain settling time should be less than ~10ns. 


  • Thank you for providing the 25MHz rate specification. Suppose I intend to adjust the gain every 40nS (25MHz). In transitioning from low to high, what is the duration for which my data must remain valid? (I want to change the data bit when latched to limit the possibility of bits not arriving at the same time.) In another way, the data would be stable/valid when the pulse is down and changes when latched. (This interface is level sensitive and not edge sensitive (rising..)?

  • The setup and hold times should apply for the parallel interface as well since they are targeted for each shift register cell. Once the hold time is elapsed, you can send the latch pulse. After the end of the latch pulse, the RF attenuator and the shift registers are disconnected.