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ADF4401A VCO stability while switching from internal to external loop

Category: Hardware
Product Number: ADF4401A

With reference to the Figure 32 (ADF4401A Evaluation Setup Block Diagram) on page 19 of ADF4401A (Rev. 0) datasheet, my queries are that when VTUNE input is switched from internal PLL to the external PFD using the switch ADG1219/ ADG1609,

1. Will the VCO frequency randomly deviate from the locked frequency (using internal PLL) during the switch transition time (~150ns for ADG1609) due to break-before-make switching or will the PLL remain in lock? There is no capacitor at the ADG1609 output to hold the VTUNE till the switching is completed (Figure 9 on Page 10 of UG-1922).

2. Will the VCO sensitivity (Kvco) determine how much the VCO will deviate during this switching period? For example in ADF4401A the VCO is multicore, so the Kvco is small, but suppose I am using HMC586 wideband VCO (4G-8G) whose sensitivity is more than 200 MHz/V will the deviation be more?

3. Is there a possibility that the external PFD will lock to an image frequency from the mixer if this momentary deviation in VCO frequency is significant? How to prevent in that case?

Please suggest