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PLL ADF4169 ringing in step-response when CSR-Bit set.

Product Number: ADF4169

I'm using ADF4169 in a PLL-circuit for generating RFsignals from 2 to 3 GHz. For shortening the settling time and for reducing spurs I want to set CSR=1 and I_CP=0. Unfortuately the frequency step response of the PLL has a strong ringing with that setting.

Here is a Schematic of the PLL-Circuit

Here are the step responses Above at CSR=1, below at CSR=0.

Any suggestions?

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  • Hi ,

    What is your RDIV/2 and reference doubler? CSR requires a 50% duty cycle to operate. Setting reference doubler and RDIV/2 bits to 1 helps to achieve a 50% duty cycle for reference.

     What is your PFD polarity?  I saw that it is positive in your screenshot, but what is the register value for PFD polarity?

    In addition to the above questions, if your Loop bandwidth is not much smaller than your PFD/10, CSR can change the phase margin. Therefore, ripple can be observed at the output?

    Thanks,

    Emrecan

  • Hi Emrecan,

    What is your RDIV/2 and reference doubler? CSR requires a 50% duty cycle to operate. Setting reference doubler and RDIV/2 bits to 1 helps to achieve a 50% duty cycle for reference.

    I initially used ReferenceDoubler=0, but ReferenceDoubler=1 and doubling RCounter has no influence on the spurs. RDIV/2 is always set 1.

    What is your PFD polarity?  I saw that it is positive in your screenshot, but what is the register value for PFD polarity?

    The register value of the PFD polarity is 1.

    In addition to the above questions, if your Loop bandwidth is not much smaller than your PFD/10, CSR can change the phase margin. Therefore, ripple can be observed at the output?

    The lock bandwidth is ca. 1MHz and PFD is 25MHz. Is this ok?

    Actually the main reason for using the CSR-mode is spurs that appear briefly at times and have an amplitude of up to -25dBc. Please see attached video.Do you have any idea what could be the cause of spurs?

    Best regards

    Mark

  • Hi Mark,

    I see that the output power of the VCO is around 4dBm. What is the signal power at the RFIN input of the ADF4159? There might be a maximum rating violation at RFIN input if there is not enough attenuation between ADF4159 and VCO. The recommended input power for RFIN is between -10dBm and 0dBm.

    Can you share the ADISimPLL file and register settings for your configuration?

    Thanks,
    Emrecan 

  • Hi Emrecan,

    it is not visible in the ADISim schematic but there is a splitter (-3,5dB) and an attenuator (-6dB) between VCO and ADF4169. So the input-power on the RFIN input is -5,5dBm,

    please find attached a text file with the PLL-setting for 2700MHz output frequency.

    # R0
    pll.setRampOn(0)
    pll.setMuxout(6)
    pll.setInt(54) # Set INT
    
    #R0/R1
    pll.setFrac(0) # Set FRAC (4697620 für 7MHz, 6375342 für 9,5MHz)
    
    #R1
    pll.setPhaseAdjuse(0)
    pll.setPhase(0)
    pll.setResR1_1(0)
    
    #R2
    pll.setCSR(0)
    pll.setCPCurrent(9)
    pll.setPrescaler(0)
    pll.setReferenceDoubler(1)
    pll.setRCounter(2)
    pll.setRDIV2(1)
    pll.setClk1Div(0)
    pll.setResR2_1(0)
    pll.setResR2_2(0)
    
    #R3
    pll.setNegBleedCurrent(0)
    pll.setNegBleedCurrentEnable(0)
    pll.setLOL(1)
    pll.setNSel(1)
    pll.setSDReset(0)
    pll.setRampMode(0)
    pll.setPSK(0)
    pll.setFSK(0)
    pll.setLDP(0)
    pll.setPDPolarity(1)
    pll.setPowerDown(0)
    pll.setCPThreeState(0)
    pll.setCounterReset(0)
    pll.setResR3_1(0)
    pll.setResR3_2(0)
    pll.setResR3_3(1)
    pll.setResR3_4(0)
    
    #R4
    pll.setLDSel(0)
    pll.setSDModulatorMode(0)
    pll.setRampStatus(0)
    pll.setClkDivMode(0)
    pll.setClkDivSel(0)
    pll.setClk2Divider(0)
    pll.setResR4_1(0)
    
    #R5
    pll.setTXDataInvert(0)
    pll.setTXDataRampClk(0)
    pll.setInterrupt(2)
    pll.setFSKRampEnable(0)
    pll.setDualRamp(0)
    pll.setDevSel(0)
    pll.setDeviationOffset(0)
    pll.setDeviation(0)
    pll.setResR5_1(0)
    pll.setResR5_2(0)
    
    #R6
    pll.setStepSel(0)
    pll.setStep(0)
    pll.setResR6_1(0)
    
    #R7
    pll.setTXDataTriggerDelay(0)
    pll.setTriDelay(0)
    pll.setSingularFullTriangle(0)
    pll.setTXDataTrigger(0)
    pll.setFastRamp(0)
    pll.setRampDelay(0)
    pll.setDelClkSel(0)
    pll.setDelStartEn(0)
    pll.setDelayStart(0)
    pll.setResR7_1(0)

    Can you give me a tip how to upload the ADISimmPLL-file. The file-type ".pll" is not allowed.

    Thanks

    Mark

  • Maybe I found a PLL-setting that solves the spur-problem:

    NegBleedCurrent=7 (R3 DB[24:22])

    NegBleedCurrentEnable=1 (R3 DB21)

    The higher the NegBleedCurrent value the lower the spurs. At 7 they are not visible anymore.

    Î still have to test if this doesn't cause any new problems like with CSR=1.

     

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  • Maybe I found a PLL-setting that solves the spur-problem:

    NegBleedCurrent=7 (R3 DB[24:22])

    NegBleedCurrentEnable=1 (R3 DB21)

    The higher the NegBleedCurrent value the lower the spurs. At 7 they are not visible anymore.

    Î still have to test if this doesn't cause any new problems like with CSR=1.

     

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