I'm using ADF4169 in a PLL-circuit for generating RFsignals from 2 to 3 GHz. For shortening the settling time and for reducing spurs I want to set CSR=1 and I_CP=0. Unfortuately the frequency step response of the PLL has a strong ringing with that setting.
Here is a Schematic of the PLL-Circuit
Here are the step responses Above at CSR=1, below at CSR=0.
Any suggestions?