HMC980LP4E
Production
The HMC980LP4E is an active bias controller that can automatically adjust the gate voltage of an external amplifier to achieve constant drain current....
Datasheet
HMC980LP4E on Analog.com
HMC998
Obsolete
Datasheet
HMC998 on Analog.com
Translation:
Hello,
Considering that the broadband distributed power amplifier HMC998APM5E has strict power-on and power-off timing requirements, and in order to reduce the variability caused by device batches,
the active bias controller HMC980LP4E was finally used to bias the HMC998APM5E.
Before I get into my problem statement, I need to make something clear: I have successfully used an HMC980LP4E to bias an HMC998APM5E, and the amplifier operates as expected, provided the
necessary power-up and power-down sequences are followed. But at the same time, I also had three questions.
1. When VIDIG is powered on first, but VDD is not powered on yet, the Vgate output terminal directly connected to the gate voltage (Vgg1) of the amplifier HMC998A will generate a continuous
and stable voltage of about +0.6V. However, the maximum withstand range of the gate voltage of the amplifier 998A is -3V~0V. At this time, when VDD is powered on, the gate voltage will drop
to near my preset value (-0.52V). At this time, all functions of the amplifier are normal. The entire performance trend can be seen in the figure below. The purple line in the figure is the
change curve of Vgate, and the yellow line and blue line are VDrain and Vgg2 supplied to the amplifier respectively. So the question is, will the +0.6V positive voltage initially generated
affect the reliability of the amplifier?
2. It may sound strange, but don’t be surprised. The problem is: because the amplifier has strict power-on and power-off timing requirements, in order to ensure its safe power-on and power-off,
I used an active bias controller HMC980LP4E to meet the requirements. However, HMC980LP4E also has its own power-on and power-off timing requirements, so how should I ensure its own timing requirements?
To sum up, the question is, why does the chip used to provide power-on and power-down sequences for other chips (mainly amplifiers) also have power-on and power-down sequences? Isn't this strange?
So I would like to ask if there is a solution to this problem, or is there a recommended circuit for using a power chip (LDO or DC-DC) to control the HMC980LP4E? If so, please provide it and just reply
with attachment.
3. Because the gate voltage tolerance range of amplifier 998A is -3V~0V, the expected gate voltage is -0.52V, which meets the default thresholds of VNEG and VGATE, which are -2.46V and -2.06V
respectively. Therefore, according to the device manual description, the relevant resistors R5~R8 for threshold control can be removed. However, after removal, the chip cannot automatically
start normally. However, if the Vneg threshold is set to -2V (R5=1.6M) and the Vgate threshold is set to -1.7V (R7=860k), the chip can start automatically normally. What is the reason for this?
Looking forward to your reply as soon as possible, thank you very much.
你好，
考虑到宽带分布式功率放大器HMC998APM5E有严格的上下电时序要求，同时为了降低器件批次带来的差异性，最终采用有源偏置控制器HMC980LP4E来偏置HMC998APM5E。
在开始我的问题陈述之前，我需要先行明确的一点是：我已经成功使用HMC980LP4E偏置HMC998APM5E，并且放大器工作在预期状态，前提是遵从必要的上下电时序。但是同时，我也产生了三个疑问。
1、先上电VIDIG，但是还未上电VDD时，直接连接放大器HMC998A栅压（Vgg1）的Vgate输出端会产生持续稳定的约为+0.6V的电压，然而放大器998A栅压的最大承受范围为-3V~0V。这个时候再给VDD上电，栅压会降至我的预设数值附近（-0.52V），此时放大器各项功能都是正常的。整个表现趋势可见下图。图中紫色线条即为Vgate的变化曲线，黄色线条和蓝色线条分别是供给放大器使用的VDrain和Vgg2。那么问题就是，开始产生的+0.6V正压会对放大器的可靠性造成影响吗？
2、听起来可能觉得小奇怪，但是勿怪。问题就是：因为放大器有严格的上下电时序要求，为了保证它的上下电安全，所以我使用了有源偏置控制器HMC980LP4E来满足要求。然而，HMC980LP4E自身也有上下电时序要求，那我又应该怎么去保证它自身的时序要求呢？总结一下问题就是，用于为其他芯片（主要是放大器）提供上下电时序的芯片自身为什么也有上下电时序，这不是显得很奇怪吗？所以我请问有解决这个问题的办法么，或者是使用电源芯片（LDO 或者DC-DC）来控制HMC980LP4E的推荐电路么？如果有，还请麻烦提供，回复挂接附件即可。
3、因为放大器998A栅压耐受范围在-3V~0V，预期栅压为-0.52V，均满足VNEG和VGATE的默认阈值，分别为-2.46V和-2.06V。所以根据器件手册描述，关于阈值控制的相关电阻R5~R8均可以移除。但是移除之后，芯片并不能正常自动启动。但是将Vneg threshold设置为-2V（R5=1.6M），Vgate threshold设置为-1.7V（R7=860k），芯片便能正常自动启动。这是什么原因呢？
期待你的尽快回复，十分感谢。
GrassKaka
Hi Grasskaka,
.
PDF
I've attached some documentation that might answer some of your questions. I will support this after you've reviewed them. Though the VDIG>VDD>VNEG sequencing is crucial for the health of the HMC980 device. I am also assuming you are using our calculator to select discrete components around the HMC980.
Thanks,
Dan
Hi，DanO2，
In the first place, I'd like to thank for your response.
Exactly as you mentioned, the peripheral circuitry for the HMC980LP4E was designed in accordance with your recommendations, which include the device datasheet HMC980LP4E, application note AN-1363, and the device calculator HMC980.xlsm. The detailed circuit schematic can be found in Figure 1.
Fig.1
The resistors R5 to R8 in the schematic are in the NC state (Not Connected). According to the 980 device datasheet , as shown in Figure 2, they can automatically initiate in their default configuration.
Fig.2
Please note that the actual situation was that, despite following the correct power-up sequence (VDIG>VDD, using internal negative voltage generation for VNEG without considering the timing), the device couldn't initiate automatically. Consequently, I further adjusted the threshold voltages for VNEG and VGATE to -2V and -1.7V, and, based on the recommended calculator, obtained the following resistor values: R5=1.6M, R6=OPEN, R7=867k, and R8=OPEN, as shown in Figure 3. After making these changes, the 980 device could finally start automatically as expected. All of these changes correspond precisely to the description of the third issue I mentioned earlier.
Fig.3
The attachment document AN-1363 (Meeting Biasing Requirements of Externally Biased RF/Microwave Amplifiers with Active Bias Controllers) that you referenced, had been thoroughly examined before commencing the design of HMC980. However, initially, I was referring to the Chinese translated version of the document. Regrettably, this translation contained some noticeable errors, particularly regarding the resistor values for R5 and R8, as can be seen in Figures 26 to 29 in the Chinese version of AN-1363. It's worth noting that these issues were only discovered later, and the original English version of the document does not have these problems.
PDFAttach.1
After mitigating the aforementioned issues (setting R5=1.6M, R6=OPEN, R7=867k, R8=OPEN), you can refer to the specific assembly diagram in Figure 4.
Fig.4
Then, by following the correct power-up and power-down sequence (ensuring manual control of the DC power supplies), the bias controller HMC980 can accurately drive the power amplifier HMC998. It operates as expected (with VDD=15.5V, VDRAIN=15V, IDRAIN=0.61A(Rsense=250Ω)，VG2_CONT=11.4V, VG2=9.64V, VNEG=-2.0V, VGATE=-0.52V, VGATE(Vgg1 for HMC998) voltage values in accordance with the HMC998 device datasheet, as shown in Figure 5).
Fig.5
Of course, this might introduce a new question regarding the voltage difference between VG2_CONT and VG2, which is 11.4V - 9.64V = 1.76V, and it doesn't match the typical value of 1.3V as mentioned in the device datasheet. While it could be attributed to device variability, one might wonder if this voltage difference is somewhat significant.
In summary, the issue regarding the power-up and power-down sequencing for HMC980 controlling HMC998 has been resolved. Now, the key concern returns to the second issue I described earlier, which is how to ensure the correct power-up and power-down sequencing for HMC980 itself (power-up with VDIG > VDD; power-down with VDD > VDIG). So, I would like to ask if there is a solution to this problem or if it's possible to use power supply chips (such as LDO or DC-DC) to control the recommended circuit for HMC980LP4E? If there is a solution, please provide it in the reply or as an attached document.
As for the first issue I mentioned earlier, I'm also looking forward to your response.
Thanks again, and I look forward to your prompt response.
GrassKaka
