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# MAX2870 or ADF4351 frequency generator

Category: Hardware

Hello everybody,

I am developing a simple signal generator from 100 MHz to 1 GHz and stumbled on these two PLL chips. They are pin compatible so for my first test i used the wider option the MAX2870. I build a custom PCB and successfuly connected the chip with my MCU (STM32) and made a simple program to set sweep frequency range and execute. This all is working well and im quite happy with it. However i would like to ask this forum with some help because i want to push the MAX2870 (or ADF4351 i dont really care which one will be used if it will solve my issue) as far as possible in order to obtain to smallest step size possible. Generally i would be happy if i could change the frequency in 100Hz steps. I dont know if this is possible or not but if yes then even lower 10 Hz step would be ideal. What have i tried is to lower the PFD frequency but lowering it below 6.25MHz makes the PLL unresponsive. Can somebody help me what to improve to obtain this kind of resolution ? Can anybody help me with loop filter optimisation and clock setup to obtain the 100 or even 10 Hz step size ?

Thank you.

Parents
• Modulus of both chips is identical, thus the minimum step is the same. In order to achieve such small step choose PLL chip with higher modulus or select low PFD frequency or make refence frequency adjustable.

• Im trying to set the PFD frequency lower but getting below 5MHz results in the PLL not locking. In the datasheet there is a maximum limit for the PFD frequency but not for the minimum. Im setting the R counter value to lower the PFD frequency according the equation fPFD = fREF O [(1 + DBR)/(R x (1 + RDIV2))]. In my case the fREF is 20Mhz, DBR is 0 and RDIV2 is 0 too. So by changing the R value from 1 to 1023 i can divide the clock for the PFD. Im also using the VAS state machine so i need to also adjust the state machine clock, fBS according to the equation BS = fPFD / 50KHz. Im doing this in code so just by changing the R all the necessary values are updated automatically. I also used the MAXIM PLL loop folter claculator to make a new loop filter but it didnt solve the problem. Im using the Frac-N option is there some limitations when using low fPFD ?

• Hi,

Now you write

When the PFD is greater than 5 MHZ the analog lock state is 0.

If i use lower fPFD the LED does not shine and the MCU is hanging on that the PLL is not locked

Something has changed? PLL unlock is now for f.PFD>5MHz?

Which registers do you modify when changing f.PFD: 20MHz -> 5MHz? Is setting of LDS and LDP (Table 2) correct?

The stability of frequency without spectrum analyzer is not easy, but you can measure with oscilloscope tuning voltage, it corresponds to output frequency. Do it carefully,  external interference must not disturb the tuning voltage, so check the meas. setup first with verified register LOCK-content, measure the stability of tuning voltage. Compare it with tuning voltage under unlock state.

If you see instability, you can reduce loop BW - redesign filter or reducing the CP current may help also.

• Sorry for the confusion. Let me clarify.

Because the analog lock detect is open collectror and requires a pullup resistor. So when locked, the transistor is open and the voltage drop on the transistor is low. So when probing the MUX output I see almost 0 V. The LD output is configured as digital lock, so when the locked, the output is high and the LED is shining.

When changing the PFD frequency im changing the R-divider register and also because im using the VAS im changing the BS register (FREQ/R)/50000) where FREQ is the ref clock and R is the R-divider value.  The  LDS and LDP is 0 and 0 because my PFD is always less than 32 MHz.

As for the tuning voltage i dont see much difference when using high PFD and the PLL is locked and lower PFD when the PLL is not showing lock state. Im using a proper 1GHz passive probe (TPP1000 - Tektronix). So I dont see VCO instability between the measurements. Next week I will have access to a spectrum analyzer so I will post here some more infromation about it. I will post here the register setup for reference. The naming and consequent registers should reflect the datasheet tables.

#define MOD 4095 // Maximum Modulus
#define FREQ 10000000 // Ref clock after division. The clock is divided already by 2 because max2870Set_RDIV2(1);
#define R 1 // R-divider value

//Register 0
max2870Set_INT(0); // Frac N
max2870Set_N(1600); // Init to some frequency i.e. 100MHz
max2870Set_FRAC(20);

//Register 1
max2870Set_CPOC(0);
max2870Set_CPL(1);
max2870Set_CPT(0);
max2870Set_P(2);
max2870Set_M(MOD); //4095 for max resolution

//Register 2
max2870Set_LDS(0); // Lock-detect speed 0 = fPFD <= 32MHz
max2870Set_SDN(0);
max2870Set_MUX(6); //MUX pin configuration = Digital lock detect
max2870Set_DBR(0); //0 = Disable reference doubler
max2870Set_RDIV2(1); //0 = Disable reference divide-by-2
max2870Set_R(R); // 1MHz f_PFD R = 10 for 10MHz clock freq
max2870Set_REG4DB(0); // Sets double buffer mode 0 = Disable
max2870Set_CP(0); //CP = 0 for VAS
max2870Set_LDF(0); // Sets lock-detect function 0 = Frac-N lock detect
max2870Set_LDP(0); // low Lock-Detect Precision 0 = 10nS
max2870Set_PDP(1); // Sets phase detector polarity 0 = Negative (for use with inverting active loop filters)
max2870Set_SHDN(0); // Sets power-down mode 0 = Normal mode
max2870Set_TRI(0); // Sets charge-pump three-state mode 0 = Disabled
max2870Set_RST(0); // Counter Reset 0 = Normal operation

//Register 3
max2870Set_VCO(0); // Manual selection of VCO and VCO sub-band when VAS is disabled.
max2870Set_VAS_SHDN(0);// Sets VAS state machine mode. 0 = VAS enabled
max2870Set_VAS_TEMP(1); // Sets VAS response to temperature drift. 1 = VAS auto-retune over temp enabled
max2870Set_CSM(0); // Reserved. Program to 000000
max2870Set_MUTEDEL(0); // Reserved. Program to 0.
max2870Set_CDM(0); // Sets clock divider mode 01 = Fast-lock enabled
max2870Set_CDIV(1); // Sets 12-bit clock divider value

//Register 4
max2870Set_SDLDO(0);
max2870Set_SDDIV(0);
max2870Set_SDREF(0);

max2870Set_FB(1);
max2870Set_DIVA(5); //Divide by 32, if 93.75MHz ≤ fRFOUTA < 187.5MHz
max2870Set_BS((FREQ/R)/50000); //BS = fPFD / 50KHz
max2870Set_SDVCO(0);
max2870Set_MTLD(0);
max2870Set_BDIV(0);
max2870Set_RFB_EN(0);
max2870Set_BPWR(0);
max2870Set_RFA_EN(0); // Begin with power off
max2870Set_APWR(0);

//Register 5
max2870Set_SDPLL(0);
max2870Set_F01(0);
max2870Set_LD(1);
max2870Set_Reserved(); // MSB of MUX

• Hello again,

I got myself a spectrum an analyzer and probed the frequency output of the PLL today. And I see nothing wrong with it. I also tried a FM demodulation of the signal using my spectrum analyzer and didnt hear anything wrong (my spectrum analyzer has only audio speaker output capability). So now im really confused why the lock detect is not provided. Right now my loop filter is 5kHz bandwidth. I could reduce it more but i have this feeling that maybe i should look for some other solution for my project. I wanted to use these PLLs as a  local oscillator for a receiver. I wanted to be able to go up to 1 GHz with good resolution. Is there some cheaper option to make this ? Because a DDS up to 1 GHz is quite expensive.

• Hi.

I checked the register content. I did not found any discrepancy, just 2 things:

1. Is the content of register 4 correct? Are reserved bits 31:29 = 0b011?
2. The table shows 2 possible settings for PFD<32MHz. Have you tried to set LPD = 0 or 1?

If you change the PDF frequency, do you adapt charge pump current? Formula for loop gain contains multiplication Icp and fPFD. Or do you always change loop filter components?

I think DDS has higher phase noise than PLL at these frequencies.

• Thank you for noticing the reserved bits. No I didnt program the 31:29 to 0b011. I added this to the code but unfortunately it didnt help. I also checked the registers bit by bit with the table to be sure there are no more wrong or unprogrammed bits. For your information this is how the PLL registers are programmed to output 100 MHz on RFout A with  9,999780 MHz (frequency corrected from 10 MHz) clock and R set to 10, MODULUS  = 4000 :

Register 0 = 0x64008c8
Register 1 = 0x2000fd01
Register 2 = 0x19029242
Register 3 = 0xb
Register 4 = 0x60d14224
Register 5 = 0x400005

On spectrum it looks like this:

When i change the R set to 1 in order to get 10 times higher  fPFD (basically it is equal to 9,999780 MHZz)  the settings are like this :

Register 0 = 0xa000e0
Register 1 = 0x2000fd01
Register 2 = 0x19005242
Register 3 = 0xb
Register 4 = 0x60dc8224
Register 5 = 0x400005

and the spectrum looks like this :

AS for the LPD settings i tried both options for  PFD<32MHz. Still no lock detect.

The charge pump current setting i do change during my test runs and when set to 0 i use the fast lock according to the datasheet. Otherwise when not using the fast lock i change the current manually between runs. I dont change the loop filter and the loop filter is designed like this :

So it should be optimized for 1 Mhz fPFD. Interestingly im getting lock detection with this loop filter for the fPFD > 5 MHz frequencies.

During my test runs without fast lock, I tried all 16 settings for the charge pump current with the 1 MHz fPFD and loop filter as shown in the picture. Still no luck.

• I have some doubts about the loop BW, 5kHz seems to me quite low. The spectral mask on the last picture has got quite high shoulder. I would propose redesign the filter for BW~25kHz, if there is not special requirement on the phase noise @ higher freq. offsets.

Next problem is your low PFD freq. When the absolute frequency difference between output frequency and PDF freq is low, you will see in the spectrum spurious (so called integer boundary spurious). I think it is visible on the  figure above (R=10) at offset = ~2kHz.

when changing the PFD freq, try to keep loop BW constant => PFD:20MHz->5MHz => Icp*=4

Otherwise the spectrum is stable, you can check the lock detect for lower PFD freq. in integer mode to recognize if there is a general problem or problem in fraction synthesis.

• I will test the ~25KHz loop filter and report what it will show.

As for the low PFD. Well i need high frequency resolution so unfortunately it has to be so low.

I dont understand your mention about the loop BW to maintain it constant. I dont intend to change the fPFD. Do i need to ? I just wanted to use the 1 MHz fPFD in the whole range from 100-1000 MHz.

I tested both integer and frac modes for low fPFD. They both dont show digital lock.

• Hi

I dont understand your mention about the loop BW to maintain it constant. I dont intend to change the fPFD. Do i need to ? I just wanted to use the 1 MHz fPFD in the whole range from 100-1000 MHz.

But you do the lock test with f.PDF<5MHz and f.PFD=20MHz. 20MHz works fine with Icp1. The loop BW=loopBW1. Try to keep it, thus if you test 5MHz, you need adjust Icp, Icp_5M=Icp_20M*4. This is what I want to say. Or vice versa. Keep konstant conditions e.g. for 1MHz and adjust Icp_20M=20*Icp_1M.

I tested both integer and frac modes for low fPFD. They both dont show digital lock.

Great. You can exclude the sigma-delta modulator and setting related to it.

• Hello again ,

after some time im back. So i designed a new filter for ~25KHz and i still dont have lock detection. I want to ask if im designing my filter correctly. See the attached file from the Maxim calculator

Also i was wondering what the t3/t1 (%) means. After some time searching online i think its the charge pump current mismatch and its related to the sink and source current matching. Now for the maxim part there is no information about the sink and source current matching but the ADF part does have it and it is 2%. Now how to input this into the designer ? As I tried to implement it i set the t3/t1 to 102 % thinking that if the t3 and t1 is qual the ratio should turn 1 or 100% so a small 2% mismatch should give 98% or 102%.

Another observation is that it doesnt really matter what filter i use (tried like 2 or 3 with various BW). It always stops indicating lock detect below 5MHz fPFD and sometimes with fPFD = 5Mhz resulting in unstable lock indication (LED indication flickering). Is there some chip design limitation im not aware of ?

• After some time searching online i think its the charge pump current mismatch and its related to the sink and source current matching

No, the T3/T1 is ratio of time constant in the 3rd order loop filter. T1 is RC constant formed by R2 and serial combination of C1, C2. T3 is time constant of R3 - C3. Well designed loop filter has got T3 lower than T1 in order not to decrease the phase margin. T3/T1 shall be 0.3 or lower.

The capacitor C3 is also quite low, parasitic capacitance of board may add significant part. R3 is high - watch thermal noise.

So i designed a new filter for ~25KHz and i still dont have lock detection

Use analog lock detect, the manual HW change on the board is not complicated.