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Noise hump on HMC738 output

Category: Hardware
Product Number: HMC738
Software Version: N/A

I am working on a project that needs to produce 40.5 GHz for molecular spectroscopy reasons. As such, I planned on using your HMC738 to generate 20.25 GHz, and then double the frequency using a standard diode doubler.

While I am able to generate these tones, I have not been able to remove what appears to be noise humps at roughly +/- 50 kHz from the nominal signal. I have already tried the following, with results listed as applicable. I'm running out of ideas to check, and would appreciate any guidance you can offer. If additional information would be helpful, please advise.

Original Schematic:

  • Sheet 1 (RF)
  • Sheet 1 (zoomed in)
  • Sheet 2 (DC Power)

Changes to Schematic in debugging:

  • 1.3V return for MCL dividers abandoned, using 150 ohms to GND instead
  • Loop filter changed to following:

Layout:

Layout (zoomed-in):

Stackup:

Current output spectrum:

 Debugging attempts:

  • On first build-up, I did not see a clean tone, but rather a clump of noise whose center frequency was where I wanted the main tone to live. Looking through old posts on this website, it appears someone else had this issue more than a year ago. After trying numerous ways to get a solitary tone,  I found that by slowly increasing the effective loop BW, I could carve out a "clean" region in the middle of this noise hump where my tone was clearly visible. At present, I believe this was due to effectively increasing the loop gain at low offset frequencies and allowing the circuit to suppress whatever noise it was picking up. However, I cannot increase the loop BW forever, as if it is noticeably higher than 1 MHz, this circuit is prone to oscillation.
  • I was initially thinking these noise clumps could be due to noise on the voltage supplies, but I don't see any evidence of this, when checking with zoomed-in oscilloscope plots. The voltage lines look reasonably clean, or at least as clean as my other electronics look.
  • Likewise, the Vtune line looks ideally calm/clean, with no obvious noise content. Moreover, the PLL (HMC699) up/down pins don't appear to be toggling at all, or at least not visibly on an oscilloscope. To be specific, they both reside at ~5V. I've confirmed the pins are not shorted together, as they diverge to 3V/5V when I remove the reference, but for whatever reason, they stay very close together and do not appear to change state when the loop is locked. This could be a red flag, as I don't recall seeing this behavior before (I've used this PLL for a different project successfully before), or perhaps it's nothing unusal.
  • After probing widely, I have yet to measure any random switching content that could produce this level of noise. I've explicitly removed the op-amp driving the IF port of the mixer, in case that was contributing, but it was not.
  • I agree the prepreg used in the board is not ideal for 40 GHz content - the choice was made in an attempt to reduce costs, given this program can accept several dB of loss due to a non-ideal dielectric. If however these noise clumps could be caused by a non-ideal dielectric choice, I'd greatly appreciate an explanation as to how that is.

Please let me know what other results I can provide. If I don't figure this out, I'll be forced to respin with a lower frequency VCO (starting at 10.125 GHz, then multiplying by 4). It is my present hope that this noise hump behavior will be less likely if I use a VCO operating at a more reasonable "Kv" tuning sensitivity, as using HMC738 at 20.25 GHz forces operation at the peak VCO sensitivity region.

Parents
  • Hi,

    Just to confirm, are you using the HMC699 for the PLL? I see in the schematic that the ADF5000 is used. I assume in SimPLL the HMC699 is used as the ADF5000 is not in the SimPLL library?

    As a debug test could you isolate multiplier and check if the direct VCO ~20GHz output has the same 50kHz bump. 

    A phase noise plot would also be of benefit if you can share this. 

    Thanks,

    Kieran 

  • Hi Kieran,

    Thanks for replying - yes, I'm using HMC699 as the main PLL, with ADF5000 providing external prescaling.

    The uploaded picture details are small, but I've already verified that the direct VCO 20.25 GHz has the 50 kHz bump (uploaded spectrum analyzer is centered at 20.25 GHz - bump content is effectively identical at 20.25 GHz & 40.5 GHz). Are you suggesting that I should try physically removing the multiplier entirely? I'd have to struggle with improvising a high frequency bypass if I still wanted to probe the output.

    I'll to upload phase noise plots this week.

    Thanks,

    Michael

Reply
  • Hi Kieran,

    Thanks for replying - yes, I'm using HMC699 as the main PLL, with ADF5000 providing external prescaling.

    The uploaded picture details are small, but I've already verified that the direct VCO 20.25 GHz has the 50 kHz bump (uploaded spectrum analyzer is centered at 20.25 GHz - bump content is effectively identical at 20.25 GHz & 40.5 GHz). Are you suggesting that I should try physically removing the multiplier entirely? I'd have to struggle with improvising a high frequency bypass if I still wanted to probe the output.

    I'll to upload phase noise plots this week.

    Thanks,

    Michael

Children
  • Yes it would be useful to try to isolate just the PLL circuit without the multiplier to ensure there is no coupling occurring. If possible can the supplies be applied externally by a clean PSU to see if this changes anything?

  • Ok - I removed the X2 multiplier, and when probing the 20.25 GHz tone capacitively above the board, the noise humps remain very clear, so it appears to be either largely or completely independent of VCO load impedance.

    The voltage supplies are currently provided from outside the board using low noise power supplies, and then locally regulated further down with standard LDO regulators. My experience suggests if we try to just use external supplies, we'll get more noise due to capacitive pickup then any we'd save by potentially using lower noise regulators. As such, I'm hesitant to try this approach, especially because I cannot measure noticeable noise on the internal voltage supplies.

  • Kieranb, your other suggestion turned out to be basically correct. While the voltage supplies were not explicitly oscillating, their noise was found to contribute to these humps on the RF carrier (in combination with the high sensitivity of the VCO, which is mostly a function of the frequency selection at 20.25 GHz). I was able to drive down the hump amplitude by ~20 dBc with more aggressive voltage regulator filtering, which should be enough for my current project.

  • That's good. I'm glad to hear this has now been resolved. 

    Thanks,

    Kieran