I am working on a project that needs to produce 40.5 GHz for molecular spectroscopy reasons. As such, I planned on using your HMC738 to generate 20.25 GHz, and then double the frequency using a standard diode doubler.
While I am able to generate these tones, I have not been able to remove what appears to be noise humps at roughly +/- 50 kHz from the nominal signal. I have already tried the following, with results listed as applicable. I'm running out of ideas to check, and would appreciate any guidance you can offer. If additional information would be helpful, please advise.
- Sheet 1 (RF)
- Sheet 1 (zoomed in)
- Sheet 2 (DC Power)
Changes to Schematic in debugging:
- 1.3V return for MCL dividers abandoned, using 150 ohms to GND instead
- Loop filter changed to following:
Current output spectrum:
- On first build-up, I did not see a clean tone, but rather a clump of noise whose center frequency was where I wanted the main tone to live. Looking through old posts on this website, it appears someone else had this issue more than a year ago. After trying numerous ways to get a solitary tone, I found that by slowly increasing the effective loop BW, I could carve out a "clean" region in the middle of this noise hump where my tone was clearly visible. At present, I believe this was due to effectively increasing the loop gain at low offset frequencies and allowing the circuit to suppress whatever noise it was picking up. However, I cannot increase the loop BW forever, as if it is noticeably higher than 1 MHz, this circuit is prone to oscillation.
- I was initially thinking these noise clumps could be due to noise on the voltage supplies, but I don't see any evidence of this, when checking with zoomed-in oscilloscope plots. The voltage lines look reasonably clean, or at least as clean as my other electronics look.
- Likewise, the Vtune line looks ideally calm/clean, with no obvious noise content. Moreover, the PLL (HMC699) up/down pins don't appear to be toggling at all, or at least not visibly on an oscilloscope. To be specific, they both reside at ~5V. I've confirmed the pins are not shorted together, as they diverge to 3V/5V when I remove the reference, but for whatever reason, they stay very close together and do not appear to change state when the loop is locked. This could be a red flag, as I don't recall seeing this behavior before (I've used this PLL for a different project successfully before), or perhaps it's nothing unusal.
- After probing widely, I have yet to measure any random switching content that could produce this level of noise. I've explicitly removed the op-amp driving the IF port of the mixer, in case that was contributing, but it was not.
- I agree the prepreg used in the board is not ideal for 40 GHz content - the choice was made in an attempt to reduce costs, given this program can accept several dB of loss due to a non-ideal dielectric. If however these noise clumps could be caused by a non-ideal dielectric choice, I'd greatly appreciate an explanation as to how that is.
Please let me know what other results I can provide. If I don't figure this out, I'll be forced to respin with a lower frequency VCO (starting at 10.125 GHz, then multiplying by 4). It is my present hope that this noise hump behavior will be less likely if I use a VCO operating at a more reasonable "Kv" tuning sensitivity, as using HMC738 at 20.25 GHz forces operation at the peak VCO sensitivity region.