Category: Software
Product Number: HMC984LP4E
I have designed a circuit for generating a 5.7 GHz frequency signal. The divider used is a series of multiple stages with a total division factor of 160. My reference frequency is 35.625 MHz. However, the CP output doesn't vary based on the phase relationship of the input signal. I can only force the CP output to be either high or low. Have anyone encountered this issue before? Seeking assistance.
