Customer issue is: reference is connected (in this case 50MHz) everything works fine… the PLL locks everything is happy. When the unit is powered up with the reference disconnected, or off, the PLL will not lock when the reference is applied.
Now, while fiddling around with the registers trying to understand them, especially reg 5, if comment out those lines, basically leaving it to defaults, the PLL works in both cases. 50 MHz present or absent during power up the PLL locks when the reference is turned on.
The datasheet is a bit cryptic on the VCO subsystem register controlled by Register 5… need some help in decoding them and understanding why they cause this behavior.
Here’s one example of the register sets the customer is using with the ADF5610…
0x01000003, // Register 0x01 = 03
0x02000001, // Register 0x02 = 01 (R)
0x05000390, // Register 0x05 = 0390 (VCO Subsystem)
0x05003E08, // Register 0x05 = 3E08 (VCO Subsystem)
0x05000000, // Register 0x05 = 00 (VCO Subsystem)
0x06002F4A, // Register 0x06 = 02F4A
0x0700094D, // Register 0x07 = 094D
0x08C9BEFF, // Register 0x08 = C9BEFF (d, bit19=1)
0x095B7FFF, // Register 0x09 = 5B7FFF
0x0A002047, // Register 0x0A = 2047
0x0B0F8061, // Register 0x0B = F8061
0x0F000081, // Register 0x0F = 0081
0x03000042, // Register 0x03 = 42 (Ni) 42 << Change this for >>
0x04600000 // Register 0x04 = 600000 (Nf) 46 << BS1 & BS2 float>>