I am using ADF4355 PLL Chip.
what is Vtune voltage of this device?
I am trying to check wheather my device is working or not because it is not locking pls help how to verify that as well.
Can you provide more information about your application? What is your reference, PFD and output frequencies? What is your loop filter? Can you also share your register configuration?
Ideally, at room temperature, Vtune should be around ~2.5V when the part is locked. When it is not locked, it can go to ~0.5V or ~4.5V.
i am using ADF 4355 for locking at CW.
VCO o/p- 6600MHz & RF o/p 3300 MHz
reference freq = 25 Mhz pulsed signal (Amplitude-4v)
PFD= 25 MHz
CP out & Vtune- 2.7v . Earlier it was 5v by default. but still rf out is 4.7 GHz with -55 dBm level but we are locking for 3.3Ghz RF out.
loop filters value.
C1-100pf; C2- 1.5nf; C3- 33pf
R1- 5.1K ; R2-11K
CE pin high with 3.3v
SPI signals- Amplitude 2 v aproxx
I would like to know why Vtune should be 2.7v when it is locked.
is logic high or this PLL is 1.8v.
Your Register 9 value seems wrong. You are setting VCO Band Division to 3 while it should be set to 11 at least. VCO Band Division value is calculated according to following formula:
f_pfd/(band division × 16) < 150 kHz which is given in Page 27 of the datasheet. You should set Reg9 to 0xB0ABCC9.
Vtune voltage range is between 0.5 V and 4.5V. At room temperature, it is expected to have a Vtune voltage that is about to mid value of the control range. This is not a digital pin.
Also, if you are aiming to get 3.3 GHz output and set the VCO freq to 6.6 GHz, you should set Register 0 to 0x201080. 0x201040 will result in 6.5 GHz VCO frequency.
i had corrected all register values as you recommended and my VTune and cp is 2.7V still its not locking to 6.6 GHz fixed vco freq and RF out is 3.3 GHz fixed.
there is (freq update sequence) in datasheet is it required to follow for fixed freq.
What is your reference source? You mentioned above that "reference freq = 25 Mhz pulsed signal (Amplitude-4v)" ? 4V amplitude is too high and we suggest to use 50% duty cycle clocks as reference. Is it possible to try a signal generator to see if this is caused by the reference?