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ADF4351 phase between outputs A and B

Category: Hardware
Product Number: ADF4351
Software Version: NA

Hello,

Sorry for the long post, but I believe some context might be helpful:

I'm currently working on an Stepped Frequency Continuous Wave Radar which uses the ADF4351 to generate both the transmitting frequency sweep (in discrete steps, to be reflected on a target) and the local oscillator for the frequency mixing on the receiver, using outputs A and B. The phase between TX and RX will provide the distance information, where the resulting I and Q values for each frequency are fed as complex numbers to an IFFT at the end of the sweep. The system is all implemented on a custom designed printed circuit board. But I'm experiencing an unexpected phase behaviour.

The mixer being used is the ADL5387, so the LO signal (ADF4351 output B) is always set to twice the frequency of output A. That is, output B is the fundamental VCO output, and output A is the VCO divided by 2, so output A is always greater than 1.1 GHz. It's also important that the phase difference between both outputs is constant for each frequency, across every sweep, even if understandably it's not zero. The phase synchronisation with the reference signal is theoretically irrelevant, as long as both RF outputs have a fixed phase difference. The LO signal into the ADL5387 is the differential output B of the ADF4351, RF input is differential too but through a balun. The ADF4351 is controlled through an Arduino's SPI interface, using a third party library.

The issue I'm having is that, every time the frequency is reconfigured, the phase between outputs A and B randomly toggles between two values which are approximately 180 degrees apart. This is inferred by reconfiguring the same frequency several times in a row, resulting in I and Q values at the mixer output which change between two voltage levels, but are symmetrical about the bias voltage. Due to this, the measured angles aren't coherent across the whole frequency sweep, which negatively affects the results. When the angle is calculated using the inverse tangent of Q/I, the angles obtained are apprx. 180 degrees apart. I know the third party library is not ideal, but in the frequency domain, the correct behaviour is observed. The PLL settles in a very short time (60 us max) compared to the sampling period, about 5 ms.

There is no fixed pattern to the phase inversion over multiple reconfigurations, and it only happens when the frequency is reconfigured by writing to the registers (with R0 last), if the output is held, the phase difference remains constant, and so do I and Q, which seems to imply the ADF4351 as the source of the issue since it only ever happens on reconfig.

To illustrate, below are the I and Q values in voltage as function of time, in a static environment, over multiple frequency sets (same frequency of RF = 1100.5 MHz), output from the ADL5387 and through a differential amplifier with unity gain and a 1.6 kHz RC low pass filter. I would expect to see here I and Q constant, ignoring the PLL settling time.

I have additionally tried using the Resynch and Phase Adjust functions (separately), with Fundamental Feedback signal, and Divided Feedback signal with neither feature, all with the same result. For the required frequency sweep, the ADF4351 operates as Fractional-N with 500 kHz steps and a 25 MHz crystal reference, with PFD frequency also at 25 MHz. I'm using Fundamental Feedback as default. The circuit used for the ADF4351 is based on the evaluation board circuit provided under the part's User Guides section, with 7.5 nH inductors to 3.3 V on each output for high frequency adaptation, and the VCO filter circuit values as is.

Shouldn't the phase between outputs A and B be constant, since both have the same signal source (VCO)? I was wondering if it could be due to the output frequency divider's unknown (to me) phase behaviour.
Is this expected behaviour from the parts involved? If so, is there a known solution through the part's configuration?

Thanks
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  • Hi,

    This is because the uncertainty coming from the divider nature. When there is a divider in a path, you cannot know the output phase of the divider. For a div by 2 block, there is two different output phase state. For a div by 4 block, there is four different output phase state. 

    When you set RFoutB to fundamental VCO output and set RFoutA to div by 2 (assuming that you are using fundamental feedback mode), you cannot determine the output phase status of RFoutA. To mitigate the uncertainty coming from RFoutA divider, you can use divided feedback mode. In that case, the rising edge of the output divider is locked to the reference rising edge and uncertainty is mitigated. When you do that, outputs of ADF4351 are always edge aligned. 

    However, there is another divider in your system, ADL5387. The div by 2 block of ADL5387 creates phase uncertainty. 

    Below is a graphical representation of the output phase states of a div by 4 block. I hope this answers the issue that you are facing. Let me know if I miss anything.

    Regards,

    Kudret

  • Hi,

    Thanks for the reply. The dividers were indeed the cause, and in the meantime has been completely fixed by choosing an equivalent mixer without LO division (ADL5382), and testing confirms the constant phase now. The explanation helped in better visualizing the problem.

    Best regards

Reply
  • Hi,

    Thanks for the reply. The dividers were indeed the cause, and in the meantime has been completely fixed by choosing an equivalent mixer without LO division (ADL5382), and testing confirms the constant phase now. The explanation helped in better visualizing the problem.

    Best regards

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