I am using HMC7044 as the clock synthesize for my hardware.
I was stuck while going through the PLL1 locking process regarding the calculation of Lock detect Timer. I tried to calculate it for the given ref clock(61.44Mhz) but could not find any relation with the PLL1 loop BW, although it is mentioned as an important criteria to select a proper value for Lock Detect Timer.
My ref clock is 50MHz, and PLL1 Loop BW is 30 Hz.
I have attached the report that I have simulated for HMC7044 using ADISimCLK tool.
Any suggestions regarding how to set a proper lock detect timer would be of much help.