HMC520A IF1/IF2 Interface schematic

Hello Masanao-San, 

I checked the datasheet and the die layout (interface schematics are part of the chip, not eval board) to compare the schematics diagram. What was provided in the datasheet is correct. We do have shunt register on IF1 and not on IF2. 

Not sure, why this is a concern for your application as this is inside the chip. Let me know if you have further questions!

Regards

Prem

Thank you for your reply, pravella-San.

I understood that this datasheet is correct.

I have an additional question.

In the "APPLICATION INFORMATION" section of the datasheet, there is a "Figure 83" that describes how to suppress Lo leakage.
Do IF1 and IF2 have any effect on this current adjustment?

Also, Please can you tell me the purpose of not designing IF1 and IF2 symmetrically?

Best regards.

Hello Masanao-San, 

Glad that your previous doubt got clarified.

There can be any number of reasons why they're not designed symmetrically. As per the datasheet plots, both IF1 and IF2 should not be much different in performance. I kindly request to evaluate our part and let you know if you find any difference in the performance. 

For your question on the current adjustment to suppress the LO leakage also, I believe it should not have any effect IF1 and IF2. Again, please evaluate our part and let us know if you find otherwise.   

Regards

Prem 

Hello. Pravella-san.

Thank you for your quick response. I understand.

If there is an impact after evaluating it, we will discuss it with you.

Best Regards.

Hello. Pravella-san.

Thank you for your quick response. I understand.

If there is an impact after evaluating it, we will discuss it with you.

Best Regards.