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EVAL-ADF4152HV Phase adjustment

Category: Software
Product Number: EVAL_ADF4152HV
Software Version: AD4150 family evaluation software (v4.4.2)

I will start off by saying I am using the EVAL-4152HV with an external Rb atomic clock (10MHz) and an external VCO (70-150 MHz). For my application it is important that I can adjust the phase of my output signal, and I wanted to quantify how much the phase of the sine wave would change based on the 'Phase Adjust' and 'Phase Value' that was input into the control software for the PLL. I am not trying to measure phase noise.

To measure the phase of my output signal I am using an oscilloscope to obtain lineouts of my RF signals. On channel one I have the same 10MHz Rb clock as is used in the PLL the second channel is the signal from the PLL. I am saving the lineouts of each channel and exporting them to fit each to a 3 parameter sine wave. Then I take the phase in radians from the fit and convert it to degrees, referencing the phase angle of the Rb clock as zero.

From the above graph you can see that there seems to be some phase control, however I wanted to know if there was any way to know what the response should be. and if I seem to be measuring phase change.

  • Hi,

    I'm not completely following your data collection/analysis methodology, but the phase adjust should be relatively straightforward to measure. Once the phase value is set and enabled, on each R0 write you will get an increase in phase difference (degrees) at the output equal to phase_adjust_value*(360/MOD). What MOD value do you have programmed?

    Another thing to note is that the SDM frac engine needs to be enabled for phase adjust to work correctly. The easiest way to do this is to ensure you're on a fractional channel. There is also a way to use phase adjust on an integer channel but it involves setting some hidden testmodes. If you need this feature let me know and I can send detail how to enable it.

    Finally, I would like to share this document - it has some useful info and tests. It's for the ADF4350, but mostly applies to ADF415x family too:

     Phase resync, phase programmability and phase coherence between multiple Fractional-N PLLs 



  • Thank you that is very helpful. I only had 2 programmed as my MOD value, because at the frequencies I am using that is the default of the eval software. 

    My follow up question is can I manually program the MOD value without changing my output frequency? That way I could have a finer phase control at the same frequency.

  • Hi,

    Yep you can adjust the MOD value as required. The MOD value is normally selected based on the PFD frequency to set the fractional channel spacing/resolution for multiple output frequency applications, but for fixed frequency applications it can be set to the lowest value that gives you the remainder needed for the fractional N value you need. Since the MOD value affects SDM operation, it also has an impact on device frac spurious. (See "Spur Mechanism" section of datasheet) and so it can be adjust to help mitigate frac spurs. Normally this is the lowest possible MOD setting as previously mentioned, since this will push the frac spurs as far from the carrier as possible which will cause them to be filtered out more by the loop filter. By default our eval software GUI will compute the lowest MOD setting.

    But the MOD setting is flexible, and can be adjusted per the use case. if you are not so worried about spurious performance you can primarily set the MOD to give you the phase adjust resolution you need. You can compensate for poor spur frac spurs by adjusting the loop filter design (lower cutoff freq or even a different topology with additional ploes/zeros). Our free tool ADIsimPLL can be used to aid in this.

  • Hi,

    I think it would be better for my application to try the phase adjustment for the integer channel, I need a relative phase change of 340 and 64 degrees (different circuits) for optimum performance. So if you could send me the the instructions or a link on how to do this, it would help a lot.

  • No problem, with the EVB software GUI if you double click the ADI logo in the bottom right corner it will bring up PLL and SD testmodes. The setting you need is in the SD testmodes to force enable frac engine even when frac = 0