i am working on ADF4355-3 EV kit. can anyone guide me how to find minimum locking time of this PLL
You can make a simulation using ADISIMPLL tool which can be downloaded from ADIsimPLL | Design Center | Analog Devices.
Total lock time is the addition of autocalibration time and loop stabilization time. You can bypass autocalibration if your application requires fast lock time, you can bypass autocalibration, details are given in AN-1353 (Rev. D) (analog.com).
Loop stabilization time depends on loop bandwidth. Wider loop bandwidth, faster lock time. All these can be simulated with ADISIMPLL. Let me know if you have any issues with ADISIMPLL.