I recently bought 2 EV-ADF4159EB1Z in order to evaluate rather the device is suited or not for an application.
The application requires that the synthesizer is able to synthesize stable CW signals in fractional-N mode as well as stable frequency ramps.
As I evaluated the CW performance of the eval board I observed that the phase noise of the PLL is "pulsating".
This is visualized by the following measurement:
The black curve is measured with a peak detector/max hold trace, while the blue one is measured with a RMS detector/avg trace.
A zero span measurement with a narrow resolution BW (3 kHz) and a small frequency offset (96 kHz) showed that this "pulsating" behavior is not random but deterministic with 2 pulses occurring every ~672 ms which is displayed in the following measurement:
That is not single pulses occurring but 2 with a small time delay is displayed in the next measurement with the same spectrum analyzer settings but different time scaling
So the phase noise of the PLL is pulsed/modulated every ~672ms by 2 pulses separated ~1.2 ms.
I've found a different thread ( RE: About the spurious noise on EV-ADF4159EB1Z) where this problem was already discussed and as a solution it was proposed to disable the SDM, which we can't do in our application.
Both of the eval boards show this error.
I already changed the power supply to rule out that this is the cause and went to an EMC friendly environment in order to rule out that the problems are caused from the "outside".
So my questions are:
Whats the cause of this problem?
Is this a general problem of the PLL(ADF4159) or caused by PCB/schematic errors?
Is it caused by other devices such as the VCO, reference oscillator or voltage regulators?
Is there a fix to this problem?
PS: My PLL settings are the default ones, the eval board has not been altered.