Cause of pulsed spurious noise/modulation on EV-ADF4159EB1Z

Question

Hello, 
 I recently bought 2 EV-ADF4159EB1Z in order to evaluate rather the device is suited or not for an application. 
 The application requires that the synthesizer is able to synthesize stable CW signals in fractional-N mode as well as stable frequency ramps. 
 As I evaluated the CW performance of the eval board I observed that the phase noise of the PLL is "pulsating". 
 This is visualized by the following measurement: 
 
 The black curve is measured with a peak detector/max hold trace, while the blue one is measured with a RMS detector/avg trace. 
 A zero span measurement with a narrow resolution BW (3 kHz) and a small frequency offset (96 kHz) showed that this "pulsating" behavior is not random but deterministic with 2 pulses occurring every ~672 ms which is displayed in the following measurement: 
 
 That is not single pulses occurring but 2 with a small time delay is displayed in the next measurement with the same spectrum analyzer settings but different time scaling 
 
 So the phase noise of the PLL is pulsed/modulated every ~672ms by 2 pulses separated ~1.2 ms. 
 I've found a different thread ( RE: About the spurious noise on EV-ADF4159EB1Z ) where this problem was already discussed and as a solution it was proposed to disable the SDM, which we can't do in our application. 
 Both of the eval boards show this error. 
 I already changed the power supply to rule out that this is the cause and went to an EMC friendly environment in order to rule out that the problems are caused from the "outside". 
 So my questions are: 
 Whats the cause of this problem? 
 Is this a general problem of the PLL(ADF4159) or caused by PCB/schematic errors? 
 Is it caused by other devices such as the VCO, reference oscillator or voltage regulators? 
 Is there a fix to this problem? 
 Best Regards. 
 PS: My PLL settings are the default ones, the eval board has not been altered.

Fullscreen 
 ADF4159_Default.txt 
 Download 
 
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33554432
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ABC123

aandrews · Accepted Answer

From what I can see this is due to SDM operation. This device can be prone to wandering spurs in frac mode too. To confirm this you can try an integer channel and disable SDM when frac = 0 using the test modes as described in that other EZ post you linked. I know that integer mode isn't sufficient for your application, but seeing if pulsing spurs are not present in int mode would be good debug to verify that this is due to the SDM. 
 I don't think there is much you can do to completely avoid this since you need frac-N operation. It is not an ADF4159 specific problem, it is inherent with the particular high bit SDM topology used here. 
 You can try experimenting with the bleed setting (reg3[24:22] and reg3[21]), we have often seen this modestly improve frac-N related spurious. Other ideas are to use a smaller MOD value if possible. Sometimes moving away from integer boundaries by adjusting the PFD frequency can also help. 
 Other newer parts have the option to change between different SDM topologies for when this SDM behaviour (if it appears) is not acceptable. For example the ADF41513 can change to a fixed, lower resolution frac mode which is less likely to exhibit behaviour like this. Unfortunately our portfolio does not include many PLLs with ramp generation built in - The ADF4159 family being the only ones we have right now. 
 Regards, 
 Alex

Electronic Design Services - PartnerZone

Cause of pulsed spurious noise/modulation on EV-ADF4159EB1Z

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