We're using your ADF4372 and can't seem to get the LEV_SEL bit to respond. The SDIO and MUXOUT pins only seem to give out 1.5V for a logic high not matter what the setting of the LEV_SEL bit? Please can you help? We seem to be able to talk to and correctly read from REG0020 only the logic high level is about 1.5V. We can read that bit being set high or low also we can force the MUXOUT pin to a high of 1.5V by setting the top four bits of REG0020 to 1000 so we're fairly confident that we have control of REG0020 but not of the LEV_SEL bit.
We note that Table 31 on page 33 of the datasheet Rev. A suggests that the default for the LEV_SEL bit is 1, similarly Table 9 on page 25, however the words on page 21 suggest different : "...both the SDIO pin and MUXOUT pin are configurable for 1.8 V (default) or 3.3 V output levels by the LEV_SEL bit setting."
We need 3.3V logic from the SDIO pin and the MUXOUT pin, please can you help?