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Individual delay when dual ramp feature enabled

Category: Datasheet/Specs
Product Number: ADF4159

Hello team,

I enabled the dual ramp feature of the PLL by setting register values as per the following

Observed the MUXOUT signal behavior in oscilloscope. The timing matched the above specifications.

But I have a question. Is it possible or is there any way to give separate delay for two ramps when PLL is in dual ramp mode?

Thanks and regards,

GAR.

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  • Hi,

    Sorry the ADF4159 does not support multiple delay timings. The ADF5902 does support this, but it contains the ADF5901 VCO and Tx chip specific for the 24GHz ISM band so may not be applicable for your use case.

    With ADF4159 you could use TxData to trigger your ramp steps individually. This is done by setting TxData ramp clock = 1. The ramp steps can be incremented by TxData pulses which allows more custom control over the how long each step takes. Please see figure 49 in datasheet for more info.

    Regards,

    Alex

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  • Hi,

    Sorry the ADF4159 does not support multiple delay timings. The ADF5902 does support this, but it contains the ADF5901 VCO and Tx chip specific for the 24GHz ISM band so may not be applicable for your use case.

    With ADF4159 you could use TxData to trigger your ramp steps individually. This is done by setting TxData ramp clock = 1. The ramp steps can be incremented by TxData pulses which allows more custom control over the how long each step takes. Please see figure 49 in datasheet for more info.

    Regards,

    Alex

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