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ADF4351 changes in R-Counter will yield different output Frequencies despite correct Int, Frac, Mod values

Category: Hardware
Product Number: adf4351

Hello all,

I am working with a custom designed receiver which uses the ADF4351 as its LO for downconversion. I followed the schematic used in the ADF4351 Eval board and wrote custom software to control the part using a Raspberry Pi. I can successfully get the part to lock onto a desired frequency which sets the lock-detect pin high. I used a spectrum analyzer to confirm the part is locked and stable. However, the frequency at which the part locks to will vary depending on the R-counter (reference divider) value I choose.

As a reference, I am using a 26 MHz clipped sine wave TXO, ECS-TXO-32CSMV-260-BN-TR, which is operating at 3.3V. I don't have a direct port to measure the reference, however, I used an oscilloscope to check I am truly getting 26 MHz out. The output to the scope didn't exactly like a clipped sine wave but I suspect its because I was using a oscilloscope probe with a ground lead attached to the outer shield of an end launch SMA attached to the board.

I can illustrate my problem through an example. When attempting to downconvert a 4 GHz RF signal to a 75 MHz baseband I am asking the ADF4351 to generate 3.925 GHz. Below I show 4 different ADF4351 configurations. In each instance the lock detect pin will go high and the part is quite stable on the spectrum analyzer (I am using a resolution BW of 30 KHz). However, only one of the configurations will yield the correct output frequency and subsequently the correct 75 MHz baseband signal. The box on the far left yields the best results. I first calculate the PFD frequency, the R-counter is set to divide the reference by 11 and the 2x and divide by 2 are bypassed. I choose INT, FRAC, and MOD values which produce a calculated RFout of 3.925 GHz, which I measure on the analyzer. However, all the other configurations shown will consistently yield different output frequencies despite using INT, FRAC, and MOD values which should generate 3.925 GHz. Also, the phase noise is quite affected as well. The phase noise is best when the part is actually able to produce the desired 3.925 GHz with the R-counter at 11, and the phase noise is worse in all other situations.

My question is, is this type of operation normal? Should I expect to see different output frequencies given different reference conditions? If so, is there a way to predict what my reference divider should be to produce my desired output frequency? If not, why might this be happening? Happy to provide more context or measured data.

Thanks in advance,

Sami

  • Hi Sami,

    MOD and FRAC values of ADF4351 is 12-bit which can take values up to 4095. In all configurations that you say it is not giving correct frequency use FRAC and MOD values higher than 4095. You should not be able to write these values to the part. 

    When I scale down your MOD values to 4095 and re-calculate the FRAC value accordingly, I am getting the frequencies you mentioned. If you use correct values for MOD and FRAC, I am sure you'll get correct frequency. 

    The other thing you may need to consider is the loop filter. Your PFD frequency is varying a lot between the configurations which causes loop response to change. I would suggest to simulate ADF4351 with your current loop filter components in ADISIMPLL. 

    Kudret