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ADF4110 RF_IN_A and RF_IN_B Differential drive

Category: Datasheet/Specs


RF_IN_A and RF_IN_B of ADF4110 are differential inputs with 500ohm resistance fixed at 1.6V. Figure 29.
Table 4. Pin Function Descriptions are shown as follows.
RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
and, RFINB should be decoupled to the ground plane with a small bypass capacitor.
This is Single-Ended drive.My question is that point.

My circuit consists of a PLL with ADF4110 and VCO as nearly shown in Fig. 33.
My VCO has a differential LVDS output. Not a Single-Ended output.

I thought it would be advantageous from the signal integrity point of view to terminate between RF_IN_A and RF_IN_B with a adjustment load resistance of less than 320 mVp-p.
Isn't it desirable to connect directly with a differential DC coupling?

Please tell me some advice.

Best regards,

  • Yes you can have a parallel 100Ohm resistor termination between differential ports if required, depending on signal levels of your source. But it is recommended to keep both RFinA and RFinB AC coupled since these ports are biased internally.

    I guess in theory you could DC couple if you were able to ensure bias is set at the required level externally (see figure 29 of datasheet), but the only reason I can think for doing this would be for lower frequency (<10MHz) operation. At RF input frequencies supported by the ADF4110, AC coupling should not be a problem. AC coupling ensures bias levels will be correct internally hence is our recommendation.



  • aandrews-san.
    Thank you very much give me answer always.

    I use it at VDD = + 3.3V.
    REFIN Input Frequency 5 MHz min / 104 MHz max For f <5 MHz, ensure SR> 100 V / µs.
    And I will input a pulse with a long update period, being careful to satisfy the slew rate of RFIN.

    Now, if I insert a DC blocking capasitor, I have to consider the Voltage Sags (Dips) issue.
    So I thought the differential DC coupling was simpler.

    The problem is the LVDS output of the 3.5mA current source,
    This is the case when 100 ohm is connected as a load between RFinA and RFinB in Fig.29.
    Will the voltage of Bias Generator 1.6V given via the internal 500ohm work properly?

    Best Regards,

  • Hi, for a LVDS output signal I would recommend AC coupling and you can probably use a voltage divider to reduce level to within ADF4110 levels - should be okay with LVDS levels. You could also use a buffer at the PLL RFinA/B input if you are worried about slew rate/voltage dips. Please see CN-0290 for more detail on this. The ADF4106 has quite a similar reference stage to ADF4110 family.



  • aandrews-san.
    Your advice was very helpful.
    My question seems to be resolved.
    Thank you very much.
    Best Regards,

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